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Browse Prior Art Database

Local Interconnect Structure and Process

IP.com Disclosure Number: IPCOM000107193D
Original Publication Date: 1992-Jan-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 3 page(s) / 86K

Publishing Venue

IBM

Related People

Henley, WB: AUTHOR [+3]

Abstract

The employment of local interconnects in a CMOS process technology provides a significant increase in the circuit density. The local interconnect provides a connection between the N+ and P+ junctions, as well as between the gate electrode and these regions without resorting to the aluminum-based wiring levels. However, previous local interconnect processes have required the use of an additional masking level and, therefore, were not self-aligned to the prior gate electrode level.

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This is the abbreviated version, containing approximately 58% of the total text.

Local Interconnect Structure and Process

       The employment of local interconnects in a CMOS process
technology provides a significant increase in the circuit density.
The local interconnect provides a connection between the N+ and P+
junctions, as well as between the gate electrode and these regions
without resorting to the aluminum-based wiring levels.  However,
previous local interconnect processes have required the use of an
additional masking level and, therefore, were not self-aligned to the
prior gate electrode level.

      This article describes a novel process for local interconnects
that does not require an additional masking level and is self-aligned
to the gate electrode level.

      The process begins following the deposition of the polysilicon
gate electrode material and the subsequent doping process.  The gate
electrode photo level is defined as in the normal process with the
addition of the local interconnection patterns connecting the N+ and
P junction regions, as shown in Fig. 1.  The polysilicon features are
anisotropically etched and the photoresist is removed afterward.  The
N+ and P+ junction regions are implanted and planarized.  The
planarization can be performed by either blanket etchback (using
photoresist) or polishing.  The contact window photo level is then
defined. The contact window level contains both, the gate electrode
and diffusion windows and the local interconnect windows. The local
interconnect windows connect th...