Browse Prior Art Database

Branch Fetch Address Table

IP.com Disclosure Number: IPCOM000107208D
Original Publication Date: 1992-Jan-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 1 page(s) / 60K

Publishing Venue

IBM

Related People

Levitan, DS: AUTHOR

Abstract

When a processor executes a branch, the processor must fetch the target instructions before it can continue execution. Currently when a branch is executed, the target address is calculated and the following cycle the cache is accessed. With a superscaler processor this puts an upper limit on performance of 2 cycles per taken branch. This invention outlines a technique to fetch the target instruction(s) at the same time the branch target is being calculated.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 65% of the total text.

Branch Fetch Address Table

      When a processor executes a branch, the processor must fetch
the target instructions before it can continue execution. Currently
when a branch is executed, the target address is calculated and the
following cycle the cache is accessed. With a superscaler processor
this puts an upper limit on performance of 2 cycles per taken branch.
This invention outlines a technique to fetch the target
instruction(s) at the same time the branch target is being
calculated.

      The Idea behind this scheme is to keep a history table of the
taken branches and that, if an instruction results in a taken branch,
then the next time the last target should be fetched instead of the
next sequential instruction(s).  If the table causes fetching down
the correct path, then there is no dead cycle for a cache access
after the branch.  This is different than a branch history table
because it is not used to predict the direction of execution of a
branch but to predict the next address to fetch.

      To implement this invention, a table is created that is
accessed by the instruction fetch address.  When a taken branch is
encountered, an entry is put into the table that identifies the
current instruction and the target address. The next time the branch
instruction is fetched, the table is accessed in parallel with the
instruction fetch and the cycle the branch is being executed the
target address is fetched.  If the instruction address is not found
in th...