Browse Prior Art Database

Prioritization of XI Request Handling

IP.com Disclosure Number: IPCOM000107247D
Original Publication Date: 1992-Jan-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 2 page(s) / 85K

Publishing Venue

IBM

Abstract

Disclosed is a technique for prioritizing the handling of crossinterrogate (XI) signals that a processor receives without impacting coherence of data in multiprocessor systems. The benefit is faster response to more urgent XI's that requires response from the processor.

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Prioritization of XI Request Handling

      Disclosed is a technique for prioritizing the handling of
crossinterrogate (XI) signals that a processor receives without
impacting coherence of data in multiprocessor systems.  The benefit
is faster response to more urgent XI's that requires response from
the processor.

      Cache coherence is a critical aspect in the design of
multiprocessor systems.  Cross-interrogate (XI) signals are typically
used for carrying out coherence operations between processors.  A
processor may receive XI signals from a central storage controller
(SC) or from other processors (and channels) directly (e.g., in a
common-bus system).  In a typical multiprocessor system with EX
states, there are two major categories of XI's:
1.   Passive - An XI that the requestor does not wait for response in
order to continue the operation that causes the XI.  A typical
example is XI-invalidate (for an unmodified line), which is a signal
requesting the invalidation of a particular cache line.  Normally the
requestor (e.g., SC) issues such an XI-invalidate in order to allow
another processor to store into the line, and response on completion
of the invalidation is generally not required.
2.   Active  -  An XI that the requestor waits for response actively.
A typical example is for the release of EX status of a cache line.
When such a line is accessed remotely, the completion of the XI
handling is normally required in order to enable the remote access.

      In conventional multiprocessor designs, XI signals are handled
in a FIFO manner at highest priority.  In (1) we observe the
opportunity of deferring XI-invalidate handling so that utilization
of free directory cycles for invalidation may be achieved.  Priority
handling of XI-in...