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High Speed Low Power BiCMOS ROM

IP.com Disclosure Number: IPCOM000107250D
Original Publication Date: 1992-Jan-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 2 page(s) / 68K

Publishing Venue

IBM

Related People

Lu, PF: AUTHOR [+2]

Abstract

Disclosed is a BiCMOS read-only memory (ROM) circuit that utilizes n-channel MOSFET for the memory cell and a bit-line current-sensing/switching technique for achieving high speed with low power. The figure shows the circuit schematics of the new memory. The n-MOSFET cell array is programmed by personalizing the drain contacts of cells (Tcell). A bit line becomes active when it is pulled up by the sensing transistor (TS) through which the cell current flows. The remaining inactive bit lines are discharged through the n-MOSFET (TSB) to the most negative supply so that only the selected bit lines consume power. When the bit line is asserted, node S switches from low to high and node SB switches from high to low to turn TSB off.

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This is the abbreviated version, containing approximately 63% of the total text.

High Speed Low Power BiCMOS ROM

      Disclosed is a BiCMOS read-only memory (ROM) circuit that
utilizes n-channel MOSFET for the memory cell and a bit-line
current-sensing/switching technique for achieving high speed with low
power.  The figure shows the circuit schematics of the new memory.
The n-MOSFET cell array is programmed by personalizing the drain
contacts of cells (Tcell).  A bit line becomes active when it is
pulled up by the sensing transistor (TS) through which the cell
current flows.  The remaining inactive bit lines are discharged
through the n-MOSFET (TSB) to the most negative supply so that only
the selected bit lines consume power.  When the bit line is asserted,
node S switches from low to high and node SB switches from high to
low to turn TSB off.  The emitter-follower action of transistor TS
with a strong base overdrive quickly charges up the bit line.  In the
meantime, one of the cells (Tcell) on the bit line is selected by
raising the word-line (gate) voltage.  If the selected cell has its
drain contact to the bit line, a large amount of current will flow
from the cell through the sensing transistors TS and reference
transistor TR, pulling the output low (read '0').  Conversely, if
there is no drain contact, only a small bleeding current flows from
the diode TN1 through the sensing transistors, and the output is
pulled to high (read '1').  Note that due to the strong VBE overdrive
during transient, a clamp diode TCL is needed to prevent t...