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Browse Prior Art Database

Self Aligned Side Gate Contact with Enhanced Contact Area

IP.com Disclosure Number: IPCOM000107259D
Original Publication Date: 1992-Feb-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 4 page(s) / 128K

Publishing Venue

IBM

Related People

Cote, DR: AUTHOR [+3]

Abstract

One of the critical challenges in producing ULSI MOSFET logic and memory chips is the production of low resistance contacts to both the gate electrodes and the source-drain junctions. As the channel length of the gate electrode and interconnects is reduced to less than 0.1 mm, the contact area available for a self-aligned contact window to the gate electrode is correspondingly reduced. Consequently, the contact resistance will be very high and the chip performance will be comprised.

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This is the abbreviated version, containing approximately 54% of the total text.

Self Aligned Side Gate Contact with Enhanced Contact Area

       One of the critical challenges in producing ULSI MOSFET
logic and memory chips is the production of low resistance contacts
to both the gate electrodes and the source-drain junctions.  As the
channel length of the gate electrode and interconnects is reduced to
less than 0.1 mm, the contact area available for a self-aligned
contact window to the gate electrode is correspondingly reduced.
Consequently, the contact resistance will be very high and the chip
performance will be comprised.

      A process technology has been developed that produces a self-
aligned contact window to the gate electrode with a significantly
larger contact area than the prior art.  After the gate conductor
stack has been deposited, a layer of Boron Nitride (BN) is deposited
by chemical vapor deposition (CVD).  The gate conductor level is
patterned by photolithography and the gate conductor stack is etched
anisotropically.  A second layer of BN is deposited at a thickness of
0.25 mm.  BN sidewall spacers are defined by a Reactive Ion Etching
(RIE) process that is selective to both the gate oxide and the under
lying silicon substrate.  This result is presented in Fig. 1.  The
N+/P+ junctions are formed and silicided by standard processing
methods.  CVD oxide is deposited and planarized to the top of the BN
cap (over the gate conductor stack) as shown in Fig. 2.  A layer of
silicon nitride of a thickness 0.15 mm is depos...