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Browse Prior Art Database

Programmable Dual Adder

IP.com Disclosure Number: IPCOM000107262D
Original Publication Date: 1992-Feb-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Mercy, BR: AUTHOR [+2]

Abstract

This chip is a high-speed, multipurpose adder/subtracter which is instrumental for developing full digital signal-processing implementations. It was designed in a project using master image technology. Fabricated in 1.0 um CMOS technology, the PDA integrates approximately 6800 logic gates on a 3.8 mm image that will operate at 25 MHz. Its effective throughput is 50 MHz. Beside providing high- speed arithmetic capabilities, the PDA also features an internal register file for intermediate data buffering, dual accumulators for sustaining high data throughput, and an On Chip Monitor (OCM) for self-test.

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Programmable Dual Adder

       This chip is a high-speed, multipurpose adder/subtracter
which is instrumental for developing full digital signal-processing
implementations.  It was designed in a project using master image
technology.  Fabricated in 1.0 um CMOS technology, the PDA integrates
approximately 6800 logic gates on a 3.8 mm image that will operate at
25 MHz.  Its effective throughput is 50 MHz.  Beside providing high-
speed arithmetic capabilities, the PDA also features an internal
register file for intermediate data buffering, dual accumulators for
sustaining high data throughput, and an On Chip Monitor (OCM) for
self-test.

      The PDA's versatile architecture, illustrated in the figure, is
conducive to various applications, such as address generation,
complex addition, and vector arithmetic. The PDA will initially be
utilized to design a highly integrated FFT engine.

      PDA chip testing will consist of several stages and will be
performed using a Taketa Ricken VLSI tester. Initially, a parametric
test will be performed on the chip to ensure proper I/O voltage and
current levels.  Next, architectural verification test patterns,
which were generated to verify the chips' architecture during
high-level modeling, will be applied to the chips' inputs to verify
that the proper responses are obtained.  Since this may not cover all
possible logic states, an additional Level-Sensitive Scan Design
(LSSD) test will be performed. LSSD testing is a de...