Browse Prior Art Database

Unique Method of Metal to Interlevel Via Self Alignment

IP.com Disclosure Number: IPCOM000107292D
Original Publication Date: 1992-Feb-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 3 page(s) / 72K

Publishing Venue

IBM

Related People

Lamey, P: AUTHOR [+3]

Abstract

One of the critical challenges facing semiconductor devices is chip size. Along with yield, these two parameters drive product cost. The die size is driven by a number of design considerations and manufacturing considerations. This article proposes a unique method to address one of the manufacturing considerations. In particular, the tolerance requirements for overlay of one masking level to another in the metallization process. Because of the silicon "real estate" must be set aside to insure proper contact between multiple levels of metallization.

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Unique Method of Metal to Interlevel Via Self Alignment

       One of the critical challenges facing semiconductor
devices is chip size.  Along with yield, these two parameters drive
product cost.  The die size is driven by a number of design
considerations and manufacturing considerations.  This article
proposes a unique method to address one of the manufacturing
considerations.  In particular, the tolerance requirements for
overlay of one masking level to another in the metallization process.
Because of the silicon "real estate" must be set aside to insure
proper contact between multiple levels of metallization.

      This article proposes a unique process to eliminate this
overlay tolerance requirement.  Once the transistors have been
defined, a planarized passivation oxide deposited and contacts
etched, a 7000 angstrom layer of aluminum/copper-silicon-titanium is
deposited.  The metal layer is then patterned using any of the
photolithographic and reactive ion etch processes known to the art.
The resultant structure is shown in Fig. 1.  After completion of this
step, a Block Via (BV) resist layer is patterned.  The BV covers
those areas where vias to the next level of metal will interconnect.
The titanium on top of the unprotected portions of the metal layer is
removed using a fluorine- based RIE process.  This process yields the
necessary selectivity for the titanium to aluminum.  The block via
structure is shown in Fig. 2.  Once the etch is complet...