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Two Port RAM Cell with Integrated Diodes

IP.com Disclosure Number: IPCOM000107294D
Original Publication Date: 1992-Feb-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 3 page(s) / 63K

Publishing Venue

IBM

Related People

Wong, RC: AUTHOR

Abstract

The conventional CTS memory cell can be extended as a two-port cell with the addition of emitters in diode configuration for high performance and high density applications. The circuitry is shown in Fig. 1 and cell layout is sketched in Fig. 2.

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Two Port RAM Cell with Integrated Diodes

       The conventional CTS memory cell can be extended as a
two-port cell with the addition of emitters in diode configuration
for high performance and high density applications.  The circuitry is
shown in Fig. 1 and cell layout is sketched in Fig. 2.

      WRITE is coupled through the emitters with the word line pull
up and bit line pull down.

      READ is coupled through the SBDs with the word line pull down
as in the CTS cells.

      During standby, the word line is at a middle level. General
operation levels are shown in Fig. 3.

      High density is accomplished with the collector integration
through the subdiffusion and base integration through the p+ base
polysilicon.  High performance is accomplished because the write oper
ation is more efficient than the HARPER cells and read operation is
the same as CTS cells.  In high-end designs HARPER cells are
generally used for fast-write and CTS cells are used for fast-read
applications.