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Fiber Optic Distributed Data Interface Network Test Adapter Page Memory Interface Circuit

IP.com Disclosure Number: IPCOM000107299D
Original Publication Date: 1992-Feb-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 3 page(s) / 125K

Publishing Venue

IBM

Related People

Eckenrode, TJ: AUTHOR [+3]

Abstract

The Page Memory Interface Circuit (PMIC) provides the electrical interconnection required to allow a RAM Buffer Controller (RBC) and a Data Path Controller (DPC) to access in excess of 256 kbytes of buffer memory. The commercially available RBC and DPC are used on a Fiber- optic Distributed Data Interface (FDDI) local area network card, but only support a maximum of 256 kbytes of memory for data buffering. In order to exceed this memory limitation, additional logic is required which is not commercially available.

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Fiber Optic Distributed Data Interface Network Test Adapter Page Memory Interface Circuit

       The Page Memory Interface Circuit (PMIC) provides the
electrical interconnection required to allow a RAM Buffer Controller
(RBC) and a Data Path Controller (DPC) to access in excess of 256
kbytes of buffer memory.  The commercially available RBC and DPC are
used on a Fiber- optic Distributed Data Interface (FDDI) local area
network card, but only support a maximum of 256 kbytes of memory for
data buffering.  In order to exceed this memory limitation,
additional logic is required which is not commercially available.

      The PMIC provides an interface between the RBC/DPC and buffer
memory to expand the addressable range of the RBC. In order to
provide this interface, the PMIC monitors various status/handshake
signals provided by the RBC and the DPC, and drives additional
address bits to the buffer memory.  In addition, an interface to a
local processor is provided which allows control by a node processor.

      The RBC manages buffer memory as three data queues: a chained
queue of asynchronous transmit data frames; a chained queue of
synchronous transmit data frames, and a first-in, first-out (FIFO)
queue of received data frames. Typically, the processor backplane
interface, for example, the IBM MICRO CHANNEL* interface, writes data
to either of the above transmit queues, and the DPC reads data from
either of the transmit queues as provided by the FDDI protocol.  The
DPC writes data into the receive FIFO queue, and the MICRO CHANNEL
interface reads data from the receive FIFO queue. In addition, the
RBC provides the node processor with random access to buffer memory.

      To support these queues, the RBC maintains several pointers.
The PMIC provides additional pointer extension bits for each pointer
maintained by the RBC and determines which pointer the RBC is using
for each buffer memory access so that it can output the correct
pointer extension bits. The PMIC makes the assumption that only one
64k x 32 bit page of buffer memory is allocated for transmit queues,
since the FDDI local area network operates at a higher data rate than
the MICRO CHANNEL interface to the card, and, therefore, a lengthy
transmit queue cannot build up during normal operation.  Thus, the
PMIC must maintain the following pointer extensions:
o    Memory Address Register (MAR) extension: set by node processor
to indicate address extension for node processor access to buffer
memory.
o    XMIT page: contains pointer extension to be used for all
transmit queue accesses.
o    Write Pointer Receive (WPR) extension: pointer extension for DPC
write access to the receive FIFO queue.
o    Read Pointer Receive (RPR) extension: pointer extension for
MICRO CHANNEL interfac...