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Browse Prior Art Database

No Fail No EC Storage Controller and Memory Card

IP.com Disclosure Number: IPCOM000107304D
Original Publication Date: 1992-Feb-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 2 page(s) / 69K

Publishing Venue

IBM

Related People

Debize, JC: AUTHOR [+4]

Abstract

Disclosed is a method being used to implement a new Storage Controller and Memory card needed to improve a Communication System provided with a maintenance processor. Several incompatible objectives are simultaneously pursued by the new design: (Image Omitted)

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 56% of the total text.

No Fail No EC Storage Controller and Memory Card

       Disclosed is a method being used to implement a new
Storage Controller and Memory card needed to improve a Communication
System provided with a maintenance processor. Several incompatible
objectives are simultaneously pursued by the new design:

                            (Image Omitted)

      First, a high quality resulting in a dramatic reduction (x100)
in the number of Repair Actions required over what is observed in the
field today for the corresponding function.

      Secondly, it is a goal of the new design to exclude any
hardware change after shipment to correct design errors.

      Thirdly, a very short time to market to respond on time to the
customer need while a limited team is available to implement the
function.

      The method makes use of Programmable Gate Arrays (PGAs)
loadable at each power-on of the system. The personalization logic is
resident on the hard disk of the machine maintenance processor. A
self-test logic, also resident on the hard disk, self tests the PGA
first after POR (Power On Reset). All Gate Arrays needed for the data
flow, address flow and control logics are duplicated. After self test
half of them are activated by the maintenace processor and a test
logic of the memory part and interconnections, resident on the hard
disk, too, is loaded. At completion of the memory and interconnection
test, the functional personalization is loade...