Browse Prior Art Database

LSSD Scan Path Verification

IP.com Disclosure Number: IPCOM000107307D
Original Publication Date: 1992-Feb-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 2 page(s) / 68K

Publishing Venue

IBM

Related People

Garcia, SE: AUTHOR [+3]

Abstract

This article describes a technique for use in a computer system which quickly verifies the integrity of level-sensitive scan design (LSSD) scan paths in Design Simulation Language/1 (DSL/1) which is a high- level language for specifying logic designs.

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LSSD Scan Path Verification

       This article describes a technique for use in a computer
system which quickly verifies the integrity of level-sensitive scan
design (LSSD) scan paths in Design Simulation Language/1 (DSL/1)
which is a high- level language for specifying logic designs.

      LSSD is a design approach which facilitates an efficient method
for very  large-scale integration (VLSI) circuit manufacturing test
generation.  To implement this approach, a stringent set of logic
rules must be followed during design entry.  A comprehensive rules
checking function, design rules checking (DRC) verifies this
compliance.

      A typical DSL/1-based chip design process proceeds as follows:
1.   Enter/edit design in high-level design language.
2.   Functionally simulate design with high-level simulator.
3.   Analyze simulation results, go to (1), if necessary.
4.   Synthesize design to target technology basic design language for
structure (BDL/S).
5.   Perform DRC on the BDL/S dataset.
6.   Analyze DRC results, go to (1), if necessary.
7.   Test generation, timing simulation, etc.

      As shown here, a process iteration resulting from DRC errors
found only at step (6) can cost time and a significant amount of
wasted CPU resources performing steps (4) and (5).  The procedure
described by this article offers a new way to alleviate this by
detecting most DRC faults prior to step (4), synthesis.

      LSSD rules require that all memory elements (i.e., shift
register latches) in a chip design be connected together in series to
form one or more shift registers which terminate at a chip...