Browse Prior Art Database

Improved Passgate Switch for FPGAs

IP.com Disclosure Number: IPCOM000107312D
Original Publication Date: 1992-Feb-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Stephens, GB: AUTHOR

Abstract

Field Programmable Gate Arrays (FPGAs) and similar devices which use NFET pass gate switches to electrically program the interconnection of logic blocks can realize improved interconnection delays by using a separately biased storage element (SRAM or latch).

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Improved Passgate Switch for FPGAs

       Field Programmable Gate Arrays (FPGAs) and similar
devices which use NFET pass gate switches to electrically program the
interconnection of logic blocks can realize improved interconnection
delays by using a separately biased storage element (SRAM or latch).

      The figure shows the schematic of a latch which is biased at a
voltage VB, which is greater than the normal VDD used to bias the
rest of the CMOS logic.  The passgate transistor which connects logic
block A to logic block B has an improved performance.

      The storage element can use non-minimum channel lengths to
avoid short channel effects since it is only switched during initial
programming.  The bias voltage can be supplied by an on-chip charge
pump or a battery since only leakage current for the storage element
is required after initial programming.