Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Floating Source Passgate Switch for FPGA Application

IP.com Disclosure Number: IPCOM000107314D
Original Publication Date: 1992-Feb-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 3 page(s) / 94K

Publishing Venue

IBM

Related People

Stephens, GB: AUTHOR

Abstract

A new CMOS floating source passgate (FSP) switch is described which can be used in field programmable gate arrays (FPGAs) instead of the single polarity passgate transistor as the switch element to electrically program the configuration of the routing of signals between logic cells in the FPGA.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Floating Source Passgate Switch for FPGA Application

       A new CMOS floating source passgate (FSP) switch is
described which can be used in field programmable gate arrays (FPGAs)
instead of the single polarity passgate transistor as the switch
element to electrically program the configuration of the routing of
signals between logic cells in the FPGA.

      The prior art passgate switch suffers from performance
degradation because its voltage swing is reduced by the transistor
threshold voltage, and because of the lack of overdrive voltage (gate
source voltage in excess of the threshold voltage) when its input is
driven with a low to high transition signal.  The gate overdrive
voltage, as well as the individual drain source voltage, is further
reduced when this type of passgate switch is used in a series
connection.

      Fig. 1 shows the schematic of the CMOS floating source passgate
switch.  The switch is turned "on" or "off" by the logic levels
applied at the nodes A and AN ("AN" = Not "A"). The A/AN level is
stored in an SRAM or scannable latch at the time of personalization
of the logical function and are both available from the same static
memory element.

      A signal applied to the input (IN0) of the switch is only
transmitted to the output when a logical "1" is applied to node A
(and a logical "0" is applied to node AN).  The output is inverted
from the input signal and is delayed by the delay through the switch.
If the opposite logical levels are applied to A/AN, the source
electrodes of Nch (Q3) and Pch (Q2) transistors are electrically
floating and the input signal is not transmitted to the output.

      The input to the switch may be connected to the input of
several such switches in the physical implementation at the time of
fabrication.  The determination of which switches transmit the signal
at the common input node is controlled by the information sto...