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Diagnosing Stuck-On Scan Clock Faults in LSSD Rings

IP.com Disclosure Number: IPCOM000107329D
Original Publication Date: 1992-Feb-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 4 page(s) / 125K

Publishing Venue

IBM

Related People

Donica, GM: AUTHOR [+3]

Abstract

A shift register latch (SRL) within a scan ring affected by a stuck-on A or B clock fault will "flush" data through itself to the next sequential latch in the ring. These LSSD scan clock stuck-on faults in multi-chip modules can be diagnosed with through-the-pins test method.

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Diagnosing Stuck-On Scan Clock Faults in LSSD Rings

       A shift register latch (SRL) within a scan ring affected
by a stuck-on A or B clock fault will "flush" data through itself to
the next sequential latch in the ring.  These LSSD scan clock
stuck-on faults in multi-chip modules can be diagnosed with
through-the-pins test method.

      During the scan ring test, a Linear Feedback Shift Register
(LFSR) can be used to compress the ring output data into a signature.
Then a simple software simulation can be performed to determine the
number of latches affected by the stuck-on clock, and, therefore,
which chip to replace on the module.

      Fig. 1 shows functional comparison of a good and faulty LSSD
ring three SRLs long.  The latch affected by the stuck-on clock
flushes and causes to ring to function exactly like a two-SRL ring.

      The diagnostic method consists of two distinct steps: (1) test
application and (2) software simulation.
1.   The deterministic test is defined in the EDS 7020 manual.  The
ring input of the device-under-test (DUT) is connected to the output
of a tester linear shift register (LSR).  The DUT ring output is
connected to the input of a tester LFSR, as shown in Fig. 2.  The DUT
scan-data-out pin of the LSSD ring to be tested is connected to a
Single Input linear feedback Shift Register (SISR).  The SISR is
seeded with zeroes.  A deterministic test data pattern is loaded into
the tester LSR and then shifted into the scan ring at the scan-input
pin by the successive application of SCAN A and B clock pairs.  These
A/B pairs are simultaneously applied to the LSR input register, the
DUT, and the SISR to create one long shift register ring.  All bits
shifted from the DUT ring into the SISR are compressed by the
feedback to form a unique signature at the completion of the test.
      Every ring will get "n" bits shifted through it, plus an exact
amount of "overshift" to form a signature in the SISR.  The signature
value is always the same for any length ring because it is
indenpendent of the length N of the DUT ring.
2.   Software Simulation
      When the collected signature is incorrect, it is necessary to
determine the number of SRLs affected by the clock fault for
diagnosis and repair.  A software program "cycles" the expected good
signature forward one bit at a time, starting with the first bit of
the deterministic input vector that would NOT have shifted into the
SISR if the ring were good.  The basic steps of the simulation are:
      a.   "Load" the good signature into the software simulated
SISR.
      b.   Shift the software SISR one bit to the right.
      c.   Calculate the value of SISR b...