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Improved Memory Availability Structure

IP.com Disclosure Number: IPCOM000107343D
Original Publication Date: 1992-Feb-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 3 page(s) / 88K

Publishing Venue

IBM

Related People

Aichelmann, FJ, Jr: AUTHOR [+2]

Abstract

A structure is proposed for low-end systems with a shared common system bus that improves the overall availability of the memory during refresh operations. This improvement is achieved by allowing the memory to defer refreshes.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Improved Memory Availability Structure

       A structure is proposed for low-end systems with a shared
common system bus that improves the overall availability of the
memory during refresh operations.  This improvement is achieved by
allowing the memory to defer refreshes.

      Conventional memory applications use either a demand refresh or
a burst refresh during idle time.  The demand defers the memory
request until refresh is completed, while the burst completes many
refreshes at one time, leaving a wide time interval available for
requests.  These methods work well with low memory utilization
applications.  This proposal utilizes a structure that will give
highest priority to memory request deferring the refresh until a
threshold limit of deferred refreshes is reached.  Once that
threshold is reached, a refresh operation can interrupt the request
and be taken.  The refresh rate is set at a faster rate to enable
this catch-up feature.

      Fig. 1 depicts a block diagram example of this low-end memory
configuration.  Fig. 2 shows a block diagram of a typical refresh
management structure.  The "memory refresh" section determines when
refresh is required, while the memory array control interfaces to the
user and memory arrays.  Fig. 3 shows the refresh structure for
improved memory availability.  The operation of this structure is
driven by a counter off a system clock which can be set externally
(via IPL, etc.) to a value which is at a refresh rate faster than the
memory array chip specification.  A comparison result (i.e., clock
and set value) is an increment in...