Browse Prior Art Database

Parallel Data Transfer Mechanism

IP.com Disclosure Number: IPCOM000107373D
Original Publication Date: 1992-Feb-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 6 page(s) / 240K

Publishing Venue

IBM

Related People

Miracle, GA: AUTHOR [+2]

Abstract

IBM System/370* I/O interface (OEMI) channels historically use delay lines and edge-sensitive DC latches which are asynchronous with the channel clocks. This article describes how an OEMI Channel extender unit implements OEMI parallel data transfer mechanism with latches and triggers with only the bus-in latches being clocked asynchronously. Provided is an OEMI parallel data transfer mechanism at the end of a fiber-optic link utilizing a latch/trigger (L/T) design with minimal edge-sensitive latches and delay lines.

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Parallel Data Transfer Mechanism

       IBM System/370* I/O interface (OEMI) channels
historically use delay lines and edge-sensitive DC latches which are
asynchronous with the channel clocks.  This article describes how an
OEMI Channel extender unit implements OEMI parallel data transfer
mechanism with latches and triggers with only the bus-in latches
being clocked asynchronously.  Provided is an OEMI parallel data
transfer mechanism at the end of a fiber-optic link utilizing a
latch/trigger (L/T) design with minimal edge-sensitive latches and
delay lines.

      This channel extender unit uses a state-machine concept for
analyzing in-tags and controlling the value of the out-tags.  Two
state-machines are used to control all interface sequences except:
interface disconnect, selective reset and system reset.  The first
state-machine, referred to as "initial selection state machine"
(ISSM), controls all initial selection sequences, ending sequences,
short busy sequences, and control-unit-initiated sequences.  The
second state- machine, the Parallel Data Transfer State Machine
(PARDXSM), controls all of the OEMI parallel data-transfer sequences.
A high-level state diagram of PARDXSM is shown in Fig. 1.  The
PARDXSM is given control by the ISSM whenever data-transfer is to
begin by setting the PARDX L/T. Resetting of the PARDX L/T or setting
of the MPINTERVEN L/T forces the PARDXSM to relinquish control of the
OEMI interface.  The ISSM also takes control of the OEMI interface
away from PARDXSM by resetting the PARDX L/T whenever Status-In rises
or Operational-In falls.  A microprocessor takes control for the
exception sequences, i.e., interface disconnect, selective reset,
etc.  Exclusive control of the OEMI interface is given to the
microprocessor whenever the MPINTERVEN L/T is active.  After control
is relinquished by the PARDXSM, the ISSM is held in a reset state
while MPINTERVEN L/T is active.

      Further explanation of the state diagram of Fig. 1 follows:
States 1, 2, 3 and C are the states that transfer data to an OEMI
control unit on write operations.  States 8, 9, A, and B are the
states that transfer data from an OEMI control unit on read
operations.  State 0 is the reset and non-controlling state.  State 4
is the state that indicates command-out stop to the OEMI control
unit.  State 7 responds to all extra data requests from the OEMI
control unit when data streaming is active.

      This channel extender unit requires delay lines for only the
Service-In and Data-In tag lines for generating clocks that Bus-In
data during read data transfers.  All interface timings and
additional delays are achieved by using internal delays or L/Ts
clocked by the system clock.

      In-tag signals go directly to a single L/T under control of the
system clock.  The Service-In, Data-In, Address-In and Status-In in-
tags are each additionally coupled to a train of three
latch/triggers.  Fig. 2 shows the Data-In tr...