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Browse Prior Art Database

Prioritized Anticipatory Arbitration

IP.com Disclosure Number: IPCOM000107378D
Original Publication Date: 1992-Feb-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 4 page(s) / 93K

Publishing Venue

IBM

Related People

Carini, R: AUTHOR [+3]

Abstract

This invention provides prioritized anticipatory arbitration for a section of memory shared by two microprocessors. The design was for a system using a Texas Instruments TMS320-C25 and a Motorola VSB 68020, but it may be customized for any two microprocessors.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Prioritized Anticipatory Arbitration

       This invention provides prioritized anticipatory
arbitration for a section of memory shared by two microprocessors.
The design was for a system using a Texas Instruments TMS320-C25 and
a Motorola VSB 68020, but it may be customized for any two
microprocessors.

      This invention is designed to perform arbitration of a block of
shared memory, giving priority to and anticipating a C25 access.  The
C25 priority means that, given a simultaneous request from both the
C25 and the 68020, the arbitration state machine will grant the C25
one access before letting the 68020 perform one access.  The
arbitration state machine anticipates a C25 access by setting up all
buffers so that the C25 has a direct link to the data buffer memory,
and can begin its memory access while the state machine is in its
idle state.  This allows C25 accesses in the minimum number of wait
states (1) dictated by the memory speed (55 ns SRAM).

      A block diagram of this invention is shown in Fig. 1, and the
state diagram of the arbitration state machine is shown in Fig. 2.

      Referring to Fig. 1, both processors have their address and
data lines multiplexed to the Data SRAM.  The 68020 has its address
latched by an ADDRESS VALID (AV) signal to insure the integrity of
the addresses throughout the memory access.  The 68020 data lines are
latched by signals VSBDATALTR and VSBDATALTW to allow the state
machine to return to its top level (state 00) before the 68020 is
done with its memory...