Browse Prior Art Database

Shared Memory Model for a Dual Processor File Server

IP.com Disclosure Number: IPCOM000107380D
Original Publication Date: 1992-Feb-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 2 page(s) / 83K

Publishing Venue

IBM

Related People

McCauley, DE: AUTHOR

Abstract

As LAN servers gain in popularity and more applications are becoming available which run on LAN systems, the demand for LAN performance is growing very rapidly. The areas in which performance is most critical are data sharing and the running of applications at the LAN server.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Shared Memory Model for a Dual Processor File Server

       As LAN servers gain in popularity and more applications
are becoming available which run on LAN systems, the demand for LAN
performance is growing very rapidly.  The areas in which performance
is most critical are data sharing and the running of applications at
the LAN server.

      There is provided a means by which multiple busmaster adapters
in a LAN server can communicate together efficiently.  This
communication takes place via two types of shared memory areas.  The
first area is for interprocessor communications.  Requests for
service between the different components of the server are passed
using request blocks stored in the interprocessor communications
area.  The second shared memory area is the data cache.  All large
data transfers between the planar processor, the coprocessor, the LAN
adapter and the disk adapter take place by passing pointers to the
data in the cache.  With this scheme, all large data transfers
between areas of system memory are avoided.

      This design provides the ability to achieve a dual-processor
server where the additional processing provided by the second
processor is not negated by additional data movement and
interprocessor communications overhead.  It enables the development
of a dual-processor file server which performs significantly less
data moves than the current uniprocessor LAN server.  This design is
only possible in a system with the capabilities, such as are
available on a Micro Channel* PS/2* computer, mainly, the ability to
have multiple busmasters, each of which is able to obtain fair access
to system memory.

      At initialization time, the dual-processor LAN server reserves
two areas of system memory.  The first area is reserved for
interprocessor communications.  The second is for data buffering and
caching.  This memory is removed from the system memory map before
the initialization of the operating system.  OS/2*, therefore, is not
known by OS/2. Only the file server knows about this memory.

      Usage of this memory is most easily described by an...