Browse Prior Art Database

Means of Adapting Existing Snoopy L1 Cache, Main Memory and I/O Subsystems for Interposition of an L2 Cache

IP.com Disclosure Number: IPCOM000107402D
Original Publication Date: 1992-Feb-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 3 page(s) / 133K

Publishing Venue

IBM

Related People

Abdulhafiz, J: AUTHOR [+6]

Abstract

An L2 cache subsystem is interposed between an L1 cache subsystem, a main memory subsystem and an I/O subsystem with only a minor change to the I/O subsystem and accompanying design components in the L2 cache subsystem. Architectural data integrity is preserved.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 51% of the total text.

Means of Adapting Existing Snoopy L1 Cache, Main Memory and I/O Subsystems for Interposition of an L2 Cache

       An L2 cache subsystem is interposed between an L1 cache
subsystem, a main memory subsystem and an I/O subsystem with only a
minor change to the I/O subsystem and accompanying design components
in the L2 cache subsystem.  Architectural data integrity is
preserved.

      A computer architecture for interconnection of system
components is shown in Fig. 1.  One or more 370 microprocessors (PUs)
with dedicated L1 cache subsystems (L1C) and a Memory Bus Adapter
(MBA) for I/O Processor (IOP) attachment share a common
command/address and data bus to main memory (memory bus).  An arbiter
exists in the PUs to determine control of the memory bus between the
MBA, PUs and L1C subsystems.  Data transfers (of either program data
or various control registers) can be initiated by the PU to/from main
memory, by the PU to/from MBA and by the MBA to/from main memory. To
preserve architectural data integrity, when the MBA references data
in main memory on behalf of an IOP, the L1 cache must be checked to
see if the latest copy of the data exists in cache rather than main
memory (i.e., the L1 cache is a "write-back" or "store-in" rather
than a "write-through" design).  This checking is performed by the
L1C via an operation whereby the L1C directory is searched using the
address presented by the MBA when a command/address is issued on the
memory bus.  This means of preserving data integrity is commonly
known as a "snoopy" L1 cache.  If a L1C directory match occurs, then,
depending on the state of the directory entry and the type of MBA
operation, the L1C will issue a command on the memory bus within a
predetermined number of memory bus cycles after the MBA command to
store the L1C line containing the data of interest to the main
memory. Meanwhile, main memory will wait this fixed number of memory
bus cycles to allow the PU time to send this command to main memory.
If this command is not received, main memory will then proceed with
the requested MBA operation.  If this command is received, the new
command cancels or postpones the original MBA operation and the new
store L1C line operation occurs instead to main memory.  In the case
where the original MBA request was a fetch, the data provided by the
L1C will be read "on the fly" as it is being stored to main memory.
In the case where the original MBA request was a store, the MBA store
operation will be delayed until the store initiated by the L1C to
main memory is completed.

      The invention described below allows introducing a new L2 cache
subsystem (L2C) and store buffer (BUF) to the system structure
described above with no logic design changes to the PUs, L1Cs, main
memory and minimal changes to the MBA.  Furthermore, the clock rate
of the interface between the PUs and L1Cs can be made a multiple of
the interface between the MBA, main me...