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Browse Prior Art Database

Unassigned Opcode Detection Mechanism

IP.com Disclosure Number: IPCOM000107404D
Original Publication Date: 1992-Feb-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 2 page(s) / 101K

Publishing Venue

IBM

Related People

Gildea, MC: AUTHOR [+3]

Abstract

Disclosed is a mechanism to efficiently detect attempted execution of unassigned opcodes of an architecture implemented on a horizontally microcoded computer.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Unassigned Opcode Detection Mechanism

       Disclosed is a mechanism to efficiently detect attempted
execution of unassigned opcodes of an architecture implemented on a
horizontally microcoded computer.

      Explicitly decoding ranges of invalid operation codes in
hardware does not allow for later support of optional facilities or
for architectural growth in the set of valid opcodes.  Also, it is a
costly approach in architectures such as ESA/390* where there are
variations in the number of bits comprising an opcode, and a lack of
discernible patterns or groups of invalid opcodes.

      Microcoded machines are more flexible in this respect.
Typically, hardware logic uses the opcode to generate the address
within control store (storage where microcode resides) of the first
word of the microprogram which implements the instruction.  For an
unassigned opcode, this first microword transfers control to an
exception handling microprogram (the 3033 and 4381 processors are
examples of designs which used this method).  Unfortunately, the
microword is wasted in the sense that it is unusable for support of
assigned opcodes.  This is an affordable side effect in machines with
large control stores, measured in terms of the quantity of microwords
provided.  However, for a machine with a limited quantity of wide
(horizontal) microwords, such "wasted" words constitute an expensive
loss.

      The mechanism described below provides the flexibility of the
microcoded approach without the normally associated cost of wasted
microwords.

      Horizontal microwords consist of a number of fields controlling
various parts of the dataflow.  A particular value of a field is
called a microorder.  A unique microorder can be designed to transfer
control to an exception handling microprogram and to additionally set
a latch indicating detection of an unassigned opcode as the reason.

      By gating such a microorder with a hardware signal that is
active only for the first microword of an instruction, the microorder
can be blocked from performing the above function when executed in
any other context.  This permits the microword containing the
microorder to perform double duty.  First, because it is located at a
control store address corresponding to an unassigned opcode, it will
detect the attempted execution of an invalid operation. Second, the
microword remains usable within other microprograms, except as the
first microword of an instruction.  By this scheme, no microwords are
dedicated (wasted) to merely...