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Comprehensive Methodology and System for AC Timing Measurements of Every Input/Output Pin Contained on a Logic Chip

IP.com Disclosure Number: IPCOM000107407D
Original Publication Date: 1992-Feb-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 4 page(s) / 124K

Publishing Venue

IBM

Related People

Combs, ML: AUTHOR [+4]

Abstract

The quality of logic and embedded memory delay testing is enhanced with the use of a "per-pin" tester. The conventional shared-resource tester can only grossly test each path while the per-pin tester can accurately measure the path delay on each pin. Disclosed is a system that allows the test data to be parsed, AC paths to be assigned and waveforms applied to every input and output (I/O) of a Level-Sensitive Scan Design (LSSD) device.

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Comprehensive Methodology and System for AC Timing Measurements of Every Input/Output Pin Contained on a Logic Chip

       The quality of logic and embedded memory delay testing is
enhanced with the use of a "per-pin" tester.  The conventional
shared-resource tester can only grossly test each path while the
per-pin tester can accurately measure the path delay on each pin.
Disclosed is a system that allows the test data to be parsed, AC
paths to be assigned and waveforms applied to every input and output
(I/O) of a Level-Sensitive Scan Design (LSSD) device.

      Logic chips that pass the stuck fault tests were found to have
failed in the field due to delay defects.  The Gross Delay
Methodology was introduced to partially detect these delay problems
by identifying a finite set of path types and then placing the tester
timing edges at known intervals so that the path delays can actually
be measured.

      The set of path delays that exist today (but are not limited
to) are based on the double-latch LSSD groundrules. These paths are
of the following logic and embedded memory categories:
      *    Primary Input to Primary Output (PI-PO)
      *    Primary Input to L1 Latch (PI-LA)
      *    L2 Latch to Primary Output (LA-PO)
      *    L2 Latch to L1 Latch (LA-LA)
      *    Primary Input to Array (PI-AR)
      *    L2 Latch to Array (LA-AR)

      The Gross Delay Methodology was introduced for implementation
on logic testers which share their limited number of timing
generators among many pins.  The test patterns are skewed and the
appropriate path timings are introduced so that this gross delay can
be measured.  This method is restricted to measuring a set of six
path types when a device may contain multiple paths of various path
lengths of each of these path types.

      The method disclosed pertains to the measurement of AC delays
on an individual I/O basis using any of a variety of a per-pin
testers.  The...