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AC Testing of Memories Embedded in LSSD Logic Using Algorithmic Pattern Generation at the Tester

IP.com Disclosure Number: IPCOM000107409D
Original Publication Date: 1992-Feb-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 5 page(s) / 151K

Publishing Venue

IBM

Related People

Forlenza, DO: AUTHOR [+4]

Abstract

As testing of VLSI chips become more complex, AC testing of these chips becomes a key factor in lowering the SPQL. Along with the increasing densities of the logic, embedded memories in an LSSD environment have become popular in high performance logic chips. Similarly, AC testing has also become a requirement for these embedded memories. Disclosed is a method for detecting the AC defects of embedded memories using Algorithmic Pattern Generation at the Tester (APG@T).

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AC Testing of Memories Embedded in LSSD Logic Using Algorithmic Pattern Generation at the Tester

       As testing of VLSI chips become more complex, AC testing
of these chips becomes a key factor in lowering the SPQL. Along with
the increasing densities of the logic, embedded memories in an LSSD
environment have become popular in high performance logic chips.
Similarly, AC testing has also become a requirement for these
embedded memories.  Disclosed is a method for detecting the AC
defects of embedded memories using Algorithmic Pattern Generation at
the Tester (APG@T).

      An embedded memory in an LSSD structure is shown in Fig. 1.
The memory is accessed through the logic such that a one-to-one
correspondence path is established on the inputs and outputs of the
memory.  Correspondence may be to the Primary Inputs (PIs), Primary
Outputs (POs) or Shift Register Latches (SRLS).  Pre-conditioning
data establishes a one-to-one path to the embedded memory. The logic
around the memory is tested using the WRP methodology, while the
embedded memory is tested with APG at the Tester.

      The invention described herein pertains to any stand-alone or
embedded memory that is tested on a logic tester with APG at the
Tester.  The operations performed on the memory are READ and WRITE
functions as shown in Figs. 2 and 3.  Unique data patterns and
addressing schemes are applied according to the predetermined types
of AC faults.

      In order to perform an AC test of the embedded memory, it must
first be isolated from the surrounding logic.  This isolation data,
which varies from part number to part number, is retrieved from the
EDS RIT data and used to float the embedded memory.  The address,
data-in, data-out and control lines of the embedded memory will be
accessed via the PIs, POs and SRLs.

      With every specific device, certain path types are known to
exist.  Logic structures consist of PI to PO, PI to Latch, Latch to
Latch and Latch to PO path types.  With the onset of embedded
memories, there are four additional path types that must be
considered.  These paths are PI to Memory, Latch to Memory, Memory to
PO and Memory to Latch.

      For discussion purposes, it will be assumed that the read
control line is always on so that the memory will be in a flush mode.
In this case there will only be two memory paths that can be measured
(PI to Memory and Latch to Memory) and the four logic paths mentioned
above may be measured through the memory.  The novelty of this
disclosure is in the structuring of an algorithmic embedded memory
test in order to produce an optimum AC test.  The following two lists
describe the sequence of operations that have been structured in a
manner that will enable the AC measurement to be performed.
      *    Read Operation
           -    Load the scan chains holding b...