Browse Prior Art Database

Instantaneous Error Detection and Isolation for Bus Multiplexer Control Logic

IP.com Disclosure Number: IPCOM000107413D
Original Publication Date: 1992-Feb-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 3 page(s) / 80K

Publishing Venue

IBM

Related People

Garofalo Jr, FJ: AUTHOR

Abstract

Disclosed is a method which provides the ability to instantaneously detect and isolate errors in the control logic of a bus multiplexer without the need for duplicate logic.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 62% of the total text.

Instantaneous Error Detection and Isolation for Bus Multiplexer Control Logic

       Disclosed is a method which provides the ability to
instantaneously detect and isolate errors in the control logic of a
bus multiplexer without the need for duplicate logic.

      In bus multiplexing logic 1 (Fig. 1), parity can be used to
detect errors in an odd number of data lines.  The errors could be
due to failures in either the data lines themselves or in the
controlling logic that only affects a portion of the bus.  More
complicated ways, such as error correction, can be used to better
detect failures in the data lines.  Failures in the control logic
which cause the wrong bus to be selected will not be detected by
these methods, since all the error detecting lines are selected along
with the data.  When the output is checked it will not show an error.

      With the conventional detection method (Fig. 2), the decoder 2
is checked by duplicating the decoder and then comparing the two
outputs with compare logic 3.  If the outputs are not the same, an
error checker is turned on.

      The method disclosed here (Fig. 3), does not use duplicate
logic, but adds "address" lines to each bus at the input to the
multiplexer 1.  The lines are tied up or down to correspond to the
select decode for each bus.  For example, if bus 1 was selected when
select control line S1 = 1 and S2 = 0, then the two input address
lines for bus 1 would be 1 and 0, respectively.  The "a...