Browse Prior Art Database

Two-Port Embedded Array Cell

IP.com Disclosure Number: IPCOM000107416D
Original Publication Date: 1992-Feb-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Barish, AE: AUTHOR [+2]

Abstract

The two-port embedded array memory cell stores 1 bit of data. It has 1 write port and 1 read port, thus allowing simultaneous write and read. The current steering write technique is used to eliminate the requirement of clamp transistors and to accomplish fast write performance. The minimum write cycle is 1 ns. The number of transistors used is 7 vs. 10 transistors required by traditional embedded array 2-port cell. The cell operates in a non-saturated mode.

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Two-Port Embedded Array Cell

       The two-port embedded array memory cell stores 1 bit of
data.  It has 1 write port and 1 read port, thus allowing
simultaneous write and read.  The current steering write technique is
used to eliminate the requirement of clamp transistors and to
accomplish fast write performance.  The minimum write cycle is 1 ns.
The number of transistors used is 7 vs. 10 transistors required by
traditional embedded array 2-port cell.  The cell operates in a
non-saturated mode.

      The schematic of the cell is shown in the figure.  T2, T3, R1,
R2 and R3 are the basic storage devices of the cell. T1, T4 and T5
form the read port.  The write port consists of transistors T6 and
T7.  C1 and C2 are used to increase the critical charge of the cell.
One current source on node SC is shared by all the cells in the same
row.

      When the read word line RWL is at logic "1", current will be
pulled from the emitter of T5.  Either T1 or T4 will be turned on and
will pull current out of node LRBL or RRBL, respectively, depending
on whether a "1" or a "0" is stored. LRBL and RRBL are connected to
the current-sense amplifier (not shown in the figure).  When current
is pulled from node LRBL, the sense amplifier output will produce a
"1".  A "0" will be generated if current is sensed in node RRBL.

      To write data into the cell, the write word line WWL and node
SC will both be at logic "1".  When SC is at "1", transistors T2 and
T3 are...