Browse Prior Art Database

Improved Page Mode Operation

IP.com Disclosure Number: IPCOM000107422D
Original Publication Date: 1992-Feb-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 3 page(s) / 79K

Publishing Venue

IBM

Related People

Aichelmann Jr, FL: AUTHOR

Abstract

A method is proposed which provides a way to extend the page mode cache operations beyond the last previously referenced address to all rows of chips, improving overall availability.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Improved Page Mode Operation

       A method is proposed which provides a way to extend the
page mode cache operations beyond the last previously referenced
address to all rows of chips, improving overall availability.

      Conventional memory applications can maintain the page mode
access method by maintaining the selected chip active until another
access involving a new RAS address is required.  This results in a
pipelined operation or page mode cache by not having to access the
chip when the same RAS address exists.  This proposal extends this
across multiple rows of chips by maintaining these previously
selected rows of chips in a standby idle state.  This method provides
a way to improve pipelining by not limiting these cache mode
operations to the last row of chips referenced.

      Fig. 1 depicts a block diagram of the memory with multiple rows
of chips (memory array elements).  Fig. 2 shows the control structure
which would be used to control and maintain the addresses of any
previously selected RAS address.  For each row of chips a separate
RAS address latch (previous cycles address latch) is compared to any
new address.  When a match is obtained with previous RAS address to a
row of chips an extended cycle is inhibited which eliminates the RAS
selection time.  Fig. 3 is a flow chart example for improving the
page mode cache operations by this method.