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Low Power Sensing Scheme with a Limited Bit Line Swing and Bit Line Multiplexing

IP.com Disclosure Number: IPCOM000107427D
Original Publication Date: 1992-Feb-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 2 page(s) / 62K

Publishing Venue

IBM

Related People

Dhong, SH: AUTHOR [+2]

Abstract

Disclosed is a new sensing scheme with a limited bit-line swing and bit-line multiplexing for low-power CMOS DRAMs. It uses a limited bit-line sensing technique with PMOS devices in source follower mode. The PMOSs, which are located next to sense amplifiers, have two functions: bit-line multiplexing and bit-line voltage limiting. This significantly reduces the number of sense amplifiers and their support circuits, while reducing the normal sensing current. The current dissipated in data retention mode is further reduced by the use of a new control method for bit-line multiplexing.

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Low Power Sensing Scheme with a Limited Bit Line Swing and Bit Line Multiplexing

       Disclosed is a new sensing scheme with a limited bit-line
swing and bit-line multiplexing for low-power CMOS DRAMs. It uses a
limited bit-line sensing technique with PMOS devices in source
follower mode.  The PMOSs, which are located next to sense
amplifiers, have two functions: bit-line multiplexing and bit-line
voltage limiting.  This significantly reduces the number of sense
amplifiers and their support circuits, while reducing the normal
sensing current.  The current dissipated  in data retention mode is
further reduced by the use of a new control method for bit-line
multiplexing.

      Fig. 1 shows the invented sensing scheme, which includes a PMOS
cell, a standard CMOS cross-coupled sense amplifier (Q1-4), PMOS
multiplexers (Q5-8), an equalizing device (Q9), and a column switch
(Q10-11).  We assume a PMOS-array DRAM in which the substrate is at
ground.  A diagram of their relative timing is shown in Fig. 2.

      When a cell stores zero data, a read operation is as follows:
After RASB falls, either PMLL or PMLR rises in order to isolate the
bit-line capacitance from the sense amplifier. If PRLL rises, a word-
line of WLR on the right side falls, and thus the signal charge
appears on BLR. Next, PS1 and PS2   activate the sense amplifier, and
thus SA and BLR pairs are  rapidly amplified.  Because the QP5 PMOS
works in source follower mode, the low-going BLR s...