Browse Prior Art Database

Packaging the Ephemeral Misses on a Line Basis

IP.com Disclosure Number: IPCOM000107430D
Original Publication Date: 1992-Feb-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 2 page(s) / 82K

Publishing Venue

IBM

Related People

Emma, P: AUTHOR [+6]

Abstract

A series of ephemeral misses can as a group be treated as a series of double words (DWs) within a single line derived by a cache miss process. Such a gather-read operation being within the capacity of a memory hierarchy provides an efficient way to satisfy the needs of the instruction that generates these misses.

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Packaging the Ephemeral Misses on a Line Basis

       A series of ephemeral misses can as a group be treated as
a series of double words (DWs) within a single line derived by a
cache miss process.  Such a gather-read operation being within the
capacity of a memory hierarchy provides an efficient way to satisfy
the needs of the instruction that generates these misses.

      The ability to monitor the transfer of the D-CACHE miss that is
caused by a particular instruction can result in the determination
that the same instruction causes another D-MISS before the transfer
is completed.  Further, the monitoring of the actual DWs within the
line that are references creates the opportunity to classify the
misses caused by such instructions to be ephemeral.  That is, such
misses are sufficiently fleeting that it is unnecessary to transfer
the line from the memory into the cache but rather to provide the DW
or DWs referenced in a line-buffer.

      A meta-miss facility coupled with an IxD prefetching as
described in U.S. Patent 4,807,110, allows the anticipation of the
next ephemeral miss and, thus, the processor can generate a request
for a series of ephemeral misses within a single miss request.  The
needs of the instruction that is generating these misses can be
satisfied by a single miss if the memory hierarchy has the ability to
perform a gather-read operation.

      As an example, consider a 128-byte line which is comprised of
16 DWs.  Consider an instruction that requires only two of the DW
within the line and can use the prefetch-chaining within the IxD
prefetching mechanism so as to determine the next eight lines.  The
total requirement for transfer being 16 DWs that can now be presented
to a buffer as the result of a single miss within the memory
hierarchy.

      The processor that issues this combined request will not only
benefit itself but benefit the memory hierarchy in terms of reducing
the set-up time for eight misses.  The process...