Browse Prior Art Database

Dual-Service Networking Protocol

IP.com Disclosure Number: IPCOM000107433D
Original Publication Date: 1992-Feb-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 3 page(s) / 147K

Publishing Venue

IBM

Related People

Pomerene, J: AUTHOR [+3]

Abstract

The memory hierarchy of processors is a fixed service network serves the processor requests in a constant unit of cache lines. Certain important processor requests can best be handled by a second network that handles double words (DWs). The creation of a DUAL-SERVICE network combines these two capabilities within a single system when the latter represent a small fraction of the overall traffic and represent requests that can be anticipated.

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This is the abbreviated version, containing approximately 42% of the total text.

Dual-Service Networking Protocol

       The memory hierarchy of processors is a fixed service
network serves the processor requests in a constant unit of cache
lines.  Certain important processor requests can best be handled by a
second network that handles double words (DWs).  The creation of a
DUAL-SERVICE network combines these two capabilities within a single
system when the latter represent a small fraction of the overall
traffic and represent requests that can be anticipated.

      Let us consider a network in which the ports are processors and
memories.  The network offers two types of service.
o    A service which involves the sending of a full cache line
      All processors have caches and all memory requests are
ostensibly performed in this quantum of accesses.  To make matters
precise, let the unit of communication between processors and
memories be a DW and let the linesize be 128 Bytes or 16 DW each
derived from the same memory.  The action of transfer of a line is to
communicate this line using the memory bus for 16 consecutive cycles.
o    A service which involves the sending of a DW

      Since a DW is part of a cache line we have the situation that
the DW will be derived from the truncated portion of the line
transfer when the line transfer has the superior service.  The
mitigating factor in such a situation, where the superior service is
offered to the cache line, is that the DW requests can be anticipated
- prefetched.  To make the point clear, a memory request that
emanates from a processor as a result of the operand fetch of an
instruction at the time it is decoded is said to have been not
anticipated.  The processor clocks his delay from the point where the
request would have come back from the cache, if a cache miss is
associated with such a request. If the access is anticipated by n
cycles, say, the request emanated from the processor n cycles prior
to the actual operand access time based on some form of prefetching
and not on actual decoding the instruction which will occur
subsequently.  Two prominent examples of DW requests that can be
anticipated are:
o   OHT MISS
      The anticipation of the miss must be derived from the
prefetching algorithm within the processor that anticipates first the
I-MISS and then is able to anticipate the concomitant D-MISS.  The
use of an I-SHADOW and the use of some IxD prefetching, as described
in U.S. Patent 4,807,110, is one approach. Another approach that is
more direct uses a table created for this purpose, the so-called OHT
(OPERAND HISTORY TABLE).  The OHT contains the Operand DW address
associated with the I-LINE that is being prefetched. Such a TABLE
generated based on historical occurrence can be an adjunct to the
I-SHADOW, that is an address maintained within the I- SHADOW.  The
I-SHADOW employs a directory larger than the one needed to support
the access to a cache as a means of trapping the changes of locality
in terms of a ch...