Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Phase Detector and Digitally Controlled Oscillator for Digital Phase Locked Loops

IP.com Disclosure Number: IPCOM000107437D
Original Publication Date: 1992-Feb-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 2 page(s) / 60K

Publishing Venue

IBM

Related People

Hutchins, RA: AUTHOR

Abstract

Disclosed is a component of an all digital Phase-Locked Loop (PLL) that produces a linear phase error as a function of the arrival time of a data pulse and operates as a digitally controlled oscillator (DCO).

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 70% of the total text.

Phase Detector and Digitally Controlled Oscillator for Digital Phase Locked Loops

       Disclosed is a component of an all digital Phase-Locked
Loop (PLL) that produces a linear phase error as a function of the
arrival time of a data pulse and operates as a digitally controlled
oscillator (DCO).

      The phase detector and DCO (PD/DCO) is a component of an all-
digital PLL as shown in Fig. 1.  The phase detector function of the
PD/DCO samples an input data bit line at a high frequency (much
greater than the nominal data rate) in order to determine where the
data pulse arrives within a bit cell.  When a data pulse arrives on
the input data bit line, the phase detector measures its arrival time
relative to the center of the bit cell and outputs a linear phase
error at the end of the bit cell.  The linear phase error is
processed by the digital PLL (not part of the PD/DCO) and a digital
number is derived that represents the desired operating frequency.
This digital number is fed back into the PD/DCO and the size of the
next bit cell or operating frequency is determined.

      The digital circuitry to implement the phase detector function
and the DCO function can be combined into a single unit as shown in
Fig. 2.  The frequency or bit cell size selection is determined by
the external digital PLL circuitry and input into the PD/DCO.  The
frequency is mapped into a counter value and loaded into a counter at
the beginning of the bit cell.  The counter is inc...