Browse Prior Art Database

Enhanced Fault Tolerance for a Crosspoint Switch

IP.com Disclosure Number: IPCOM000107438D
Original Publication Date: 1992-Feb-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 3 page(s) / 103K

Publishing Venue

IBM

Related People

Bjornseth, PJ: AUTHOR [+2]

Abstract

With existing CMOS technologies, the design of a crosspoint matrix switch structure is typically bounded by chip I/O, not by internal cell count limitations. A design has been developed which takes advantage of the surplus internal cell area on a CMOS matrix switch chip to enhance the availability of the switch in the case of certain internal chip failures.

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Enhanced Fault Tolerance for a Crosspoint Switch

       With existing CMOS technologies, the design of a
crosspoint matrix switch structure is typically bounded by chip I/O,
not by internal cell count limitations.  A design has been developed
which takes advantage of the surplus internal cell area on a CMOS
matrix switch chip to enhance the availability of the switch in the
case of certain internal chip failures.

      Two approaches to crosspoint switch design will be presented to
show the advantages of fully replicating the internal switch design
when the necessary cell area is available.  The one-sided crosspoint
switch, allows for multiple internal failures in a given switch chip
due to the inherent redundancy offered by its vertical conduction
paths.  However, if a single fault occurs within a significant part
of the data path, or any of the control logic, an unrecoverable
switch error will exist, resulting in a loss of some or all
connectivity through the switch.

      The amount of cell space providing the redundant vertical
conduction path function, as a percentage of total internal chip
area, may be as low as 30%, based on design implementation.  This
means that a fault occurring in as much as 70% of the used cell area
will cause performance degradation of the one-sided switch.

      The conventional two-sided switch design, implementing a spare
column, provides better recovery from single failures than the one-
sided design.  A failure in approximately 55% of the internal cell
area used to implement this design will cause a degradation of switch
performance.  If an upper bound exists for the number of devices to
be supported by the switch, the two-sided design is more efficient
and reliable, when implemented in a typical CMOS technology.

      Neither the one- nor the two-sided approach offers the amount
of failure protection required in a critical communications network.
The switch, being the central part of a communications network, must
not cause a loss of connectivity between attached devices.  This
warrants the need for the most efficient, practical redundancy
technique feasible for a dense technology.  This requirement led to
the full replic...