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Browse Prior Art Database

Multilayer Construction Technique for PCB

IP.com Disclosure Number: IPCOM000107447D
Original Publication Date: 1992-Feb-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 1 page(s) / 43K

Publishing Venue

IBM

Related People

Hermann, K: AUTHOR [+3]

Abstract

Disclosed is a technique for constructing a multilayer printed circuit board (PCB). Two printed circuit board layers, each consisting of two signal planes and one reference plane (2S1P), are laminated with an intermediate third layer. The third layer (item 1) is composed of a carrier having small holes therein of a size compatible with the 2S1P layers and filled with solder paste. Pressure is applied and the temperature of the solder paste is elevated. Thus, the three 2S1P layers (items 2, 3 and 4), when properly aligned and will become bonded electrically connected with the intermediate layers 1 and 5.

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This is the abbreviated version, containing approximately 100% of the total text.

Multilayer Construction Technique for PCB

      Disclosed is a technique for constructing a multilayer printed
circuit board (PCB).  Two printed circuit board layers, each
consisting of two signal planes and one reference plane (2S1P), are
laminated with an intermediate third layer.  The third layer (item 1)
is composed of a carrier having small holes therein of a size
compatible with the 2S1P layers and filled with solder paste.
Pressure is applied and the temperature of the solder paste is
elevated. Thus, the three 2S1P layers (items 2, 3 and 4), when
properly aligned and will become bonded electrically connected with
the intermediate layers 1 and 5.

      Disclosed anonymously.