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Browse Prior Art Database

Fuse Resistance Monitor

IP.com Disclosure Number: IPCOM000107458D
Original Publication Date: 1992-Feb-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 1 page(s) / 37K

Publishing Venue

IBM

Related People

Akrout, CC: AUTHOR [+2]

Abstract

Resistance of a variable resistance fuse element is determined as being high (selectively preheated) or low (unheated) by this sensing circuit which provides a high or low DC output signal without consuming DC power.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Fuse Resistance Monitor

      Resistance of a variable resistance fuse element is determined
as being high (selectively preheated) or low (unheated) by this
sensing circuit which provides a high or low DC output signal without
consuming DC power.

      Referring to the circuit diagram in the figure, a
complementary-metal-oxide-silicon (CMOS) latch is comprised of P-type
transistors T1 and T2 and N-type transistors T3 and T4.  Transistor
T6 is used to initialize the latch via input signal IN.  Transistor
T5 is used to isolate fuse F from the latch.  State of the latch may
be read at output OUT.

      As shown in the timing diagram, a single shot initializing
pulse IN is provided during system power up (rising VH level).  Then,
during sense pulse S, a "1" is written into the latch if resistance R
of fuse F is low and the latch remains at "0" if resistance R of
fuse F is high. State of the latch may be read thereafter at output
OUT.

      Disclosed anonymously.