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Enhanced Density Folded Bit Line Array

IP.com Disclosure Number: IPCOM000107459D
Original Publication Date: 1992-Feb-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 1 page(s) / 52K

Publishing Venue

IBM

Related People

DeBrosse, JK: AUTHOR

Abstract

By means of a slanted bit line array layout, an open bit line type of dynamic random access memory cell is wired in a folded bitline arrangement. This architecture results in achieving the low noise and good sense amplifier pitch of a folded bit line array while maintaining high cell density.

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Enhanced Density Folded Bit Line Array

      By means of a slanted bit line array layout, an open bit line
type of dynamic random access memory cell is wired in a folded
bitline arrangement.  This architecture results in achieving the low
noise and good sense amplifier pitch of a folded bit line array while
maintaining high cell density.

      Referring to the figure, wordlines WL are arrayed parallel
vertically and make contact to transfer devices as shown.  Bitlines
BL1T and BL1C are formed of first level metal and are stepped across
the array of wordlines WL making bit line contacts as shown.
Bitlines BL2T and BL2C are formed of second level metal, run parallel
at a 14-degree angle to the perpendicular with wordlines WL, and make
bit line contacts as shown.

      At a slight cost in bitline length, array rectangularity may be
maintained by dividing the array into segments wherein bitlines are
alternately slanted downward, then upward.

      Although bit line pairs are on the same metallurgy level and
are therefore capacitively balanced, first level bit line pairs are
not identical to second level bitline pairs.  To avoid fast and slow
setting pairs, bit line segments may be connected so that all bit
lines consist of half first level and half second level segments.
Proper connection of the bit line segments can provide many of line
to line coupling reduction benefits realized in twisted bit line
arrangments.

      Disclosed anonymously.