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Browse Prior Art Database

Process to Make Thick and Thin Gate Dielectric Devices on the Same Chip

IP.com Disclosure Number: IPCOM000107460D
Original Publication Date: 1992-Feb-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 1 page(s) / 47K

Publishing Venue

IBM

Related People

Batey, J: AUTHOR [+5]

Abstract

By process modification, thin dielectric, low voltage field-effect devices are made on the same chip with thicker dielectric, higher voltage devices.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Process to Make Thick and Thin Gate Dielectric Devices on the Same Chip

      By process modification, thin dielectric, low voltage
field-effect devices are made on the same chip with thicker
dielectric, higher voltage devices.

      Referring to Fig. 1, standard processing is used to form
shallow trench isolation oxide 2 which surrounds a region designated
for construction of thick oxide, high voltage devices (HVDs), and
thin gate dielectric 4 on substrate 6.  Then, highly doped
polysilicon 8 is deposited and etched to expose dielectric 4 in HVD
regions and left to cover LVD regions.  Next, ion implantation is
performed to tailor turn- on voltage (Vt) of HVDs.  Dielectric 4 may
be removed from HVD regions after the implant.

      Referring to Fig. 2, conformal dielectric layer 10 and then
highly doped polysilicon layer 12 are deposited and planarized until
polysilicon 8 is again exposed.  Silicide layer 14 is formed next to
electrically connect polysilicon 8 and 12.  Standard processing is
resumed wherein gate electrodes for LVDs having gate dielectric 4 are
comprised of silicide 14 and polysilicon 8.  HVDs have gate
dielectric 10 and gate electrodes formed in silicide 14 and
polysilicon 12.

      The process is adaptable to fabrication of both N and P type
devices.

      Disclosed anonymously.