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Clustered Reactive Ion Etching Process for 0.1 Micron Gate Polysilicon

IP.com Disclosure Number: IPCOM000107479D
Original Publication Date: 1992-Feb-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 1 page(s) / 48K

Publishing Venue

IBM

Related People

Rishton, SA: AUTHOR [+2]

Abstract

Disclosed is a method for etching narrow polysilicon gate lines. The method utilizes a thin dielectric stack to pattern the lines. One of the critical steps involved is the pattern transfer from the resist to the dielectric stack. A non-selective dielectric process, such as using CF4 plasma, is used to etch the dielectric stack. A polymerizing process, such as using CHF3-based chemistry, may lead to profile tapering due to polymer deposition on the polysilicon sidewall. This can result in the growth of the critical dimension. Once the dielectric stack is patterned, the resist can be removed or ignored due to the use of a selective process that follows.

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Clustered Reactive Ion Etching Process for 0.1 Micron Gate Polysilicon

      Disclosed is a method for etching narrow polysilicon gate
lines.  The method utilizes a thin dielectric stack to pattern the
lines.  One of the critical steps involved is the pattern transfer
from the resist to the dielectric stack.  A non-selective dielectric
process, such as using CF4 plasma, is used to etch the dielectric
stack.  A polymerizing process, such as using CHF3-based chemistry,
may lead to profile tapering due to polymer deposition on the
polysilicon sidewall.  This can result in the growth of the critical
dimension.  Once the dielectric stack is patterned, the resist can be
removed or ignored due to the use of a selective process that
follows.

      Following the patterning of the thin dielectric stack, the
sample is transferred to a polysilicon under vacuum. The polysilicon
etch is a two-step process.  The first process is a directional etch
with CL2/HBr chemistry. Chlorine emission line is used for the
end-point detection. The second step uses a mixture of Cl2/HBr/O2
which is very selective to the underlying oxide.  This step is used
to remove the remaining polysilicon left unetched.  The control
overetching is important to achieve a desired profile.  An excessive
overetching will result in profile degradation. For a given
polysilicon thickness, device topography, and an overetching
requirement, an adjustment in the selectivity, i.e., by adjusting the
gas mixture...