Browse Prior Art Database

Delayed ECC Correction

IP.com Disclosure Number: IPCOM000107491D
Original Publication Date: 1992-Feb-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 1 page(s) / 56K

Publishing Venue

IBM

Related People

Carnevale, MJ: AUTHOR [+4]

Abstract

An invention for ECC (Error Correction Code) support in an LSSD (Level-Sensitive Scan Design) design is disclosed. The invention allows a DRAM controller in an LSSD design to support ECC without adding extra delay for correction logic in all cycles.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 83% of the total text.

Delayed ECC Correction

      An invention for ECC (Error Correction Code) support in an LSSD
(Level-Sensitive Scan Design) design is disclosed.  The invention
allows a DRAM controller in an LSSD design to support ECC without
adding extra delay for correction logic in all cycles.

      A common practice on memory controller designs is to use extra
DRAM modules and store Error Correction Code (ECC) bits with the data
so that memory errors can be detected and single bit errors can be
corrected.  Another common practice is to route the memory data and
ECC bits through ECC error detection and correction logic before the
data is used. However, continuously routing data through detection
AND correction logic will induce delay in the memory paths (see the
figure).

      To reduce this delay in an LSSD design, the invention takes
advantage of the fact that an ECC error condition can be detected
much quicker than it can be corrected.  A mux is added so that only
if an error occurs will the delay of the ECC correction logic enter
the critical path.  This can be done by gating the B clock of the
system so that, in the event of an ECC error, the system "misses a
beat" while the data is routed through the ECC correction logic.  If
no error is encountered, the mux selects the raw data from the DRAM
to enter the data latch.

      The advantage of gating the B clock over the C clock is that it
occurs later in time than the C clock.  This allows the error
detection l...