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Browse Prior Art Database

Area Array Attach

IP.com Disclosure Number: IPCOM000107499D
Original Publication Date: 1992-Feb-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 1 page(s) / 45K

Publishing Venue

IBM

Related People

Dixon, JC: AUTHOR [+3]

Abstract

The intent of this disclosure is to describe a cost-effective method for improving wiring density of printed circuit technology.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 94% of the total text.

Area Array Attach

      The intent of this disclosure is to describe a cost-effective
method for improving wiring density of printed circuit technology.

      The current state-of-the-art of the two layer TAB technology is
2.5 mil lines on 4.5 mil centers.  TAB requires 1 oz. copper (1.4 mil
thick lines) to provide mechanical strength for the leads that bond
the chip and the package to the card.  If the metal thickness is
reduced 0.5 mil, it is feasible to produce 1 mil lines on 3 mil
centers. Bonding the film to the card in an Area Array format
eliminates the requirement for thick copper for mechanical lead
strength.  Utilizing this enhanced wiring capability, a wiring layer
can be built with the TAB technology that will allow the
interconnection of a chip to a via pattern on 50 x 50 mil grid, which
matches the via grid on a printed wiring card.

      Via holes can be formed in the tape structure on the 50 mil
grid.  Vias can be formed in several ways - punching, drilling or
etching techniques.  The vias can then be seeded and plated.  TAB
tape can have two sided metallurgy, so bottom side metal (e.g., as
for ground or reference plane) can be employed.

      The tape structure is placed on a printed circuit wiring card
and joined to the card by solder reflow. Screened solder,
thermo-compression bonding of the vias using the lands around the via
holes, placing a pin through the via of the tape structure into the
card and solder in place, and a press...