Browse Prior Art Database

Scalable, Modular, Interconnection Cache Network Structure for Temporarily Localized Communication Requests

IP.com Disclosure Number: IPCOM000107526D
Original Publication Date: 1992-Mar-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 3 page(s) / 125K

Publishing Venue

IBM

Related People

Georgiou, CJ: AUTHOR [+3]

Abstract

Disclosed is a high performance interconnection structure that minimizes the network control and contention resolution delays of large interconnection networks, by separating the network connectivity from control (reconfiguration). The disclosed structure has two components, as shown in the figure: 1. An input (and, optionally, an output) mapping unit that is a large non-blocking, circuit-switched network with as few stages as possible. 2. Several intermediate, small packet switching networks, called interconnection caches, that have fast control.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Scalable, Modular, Interconnection Cache Network Structure for Temporarily Localized Communication Requests

       Disclosed is a high performance interconnection structure
that minimizes the network control and contention resolution delays
of large interconnection networks, by separating the network
connectivity  from control (reconfiguration). The disclosed structure
has two  components, as shown in the figure:
1.   An input (and, optionally, an output) mapping unit that is a
large non-blocking, circuit-switched network with as few stages as
possible.
2.   Several intermediate, small packet switching networks, called
interconnection caches, that have fast control.

      The internal structure of each component varies, depending on
the network size and the available basic switching chips. As
different types of chips are needed, each incorporating different
functions, there are several possibilities for the construction of
the network components.

      The mapping input and output units can be, for example, either
a crossbar or a multi-stage network. As the basic "switch building
block" used for the mapping unit does not need to incorporate  smart
functions (control, buffers, etc.), the number of levels (stages)
needed for a certain network size can be minimized.  The mapping
units, which operate as circuit switches, introduce the minimum
possible delay to the data transfers.  Specifically, this latency
consists of only the signal propagation time through the mapping
unit; there is no logic processing of the data.

      The interconnection caches are used in "strategic" places to
distribute the network control problem for most of the time (after
the initial setting of the mapping units). The network control
problem is reduced from arbitration between N ports to arbitration
between a much smaller number of ports n handled by each of the
interconnection caches. If the time window, during which the
communication requests by a port are localized, is relatively long
compared to the time needed to establish connections in the mapping
unit, only the interconnection caches are involved in the
reconfiguration process. Therefore, the time to reconfigure the
network is proportional to the amount of local connectivity each port
has.  The cost of the network described is small, as only part of it
(the interconnection caches) use "smart" switching elements which
require very fast and complex control logic.

      For the network operation it is assumed that the connectivity
of each port i...