Browse Prior Art Database

Technique to Allocate Space on VLSI Chips for Design Changes

IP.com Disclosure Number: IPCOM000107528D
Original Publication Date: 1992-Mar-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 2 page(s) / 71K

Publishing Venue

IBM

Related People

Doyle, JJ: AUTHOR [+2]

Abstract

A method for distributing unused space on a VLSI chip is disclosed. The method is included in a circuit placement program by way of a metric which describes this space in mathematical terms. The unused space can be used for future engineering changes. (Image Omitted)

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This is the abbreviated version, containing approximately 52% of the total text.

Technique to Allocate Space on VLSI Chips for Design Changes

       A method for distributing unused space on a VLSI chip is
disclosed.  The method is included in a circuit placement program by
way of a metric which describes this space in mathematical terms.
The unused space can be used for future engineering changes.

                            (Image Omitted)

      This method defines a metric, called cell balancing, which is
included in the circuit placement program along with other metrics,
such as wiring congestion and wire length.  Its intent is to keep a
small percentage of open area everywhere on the chip.  For example,
if no area on the chip exceeds 90 percent full, there is a high
probability that last-minute circuit additions can be inserted
without moving previously placed circuits.

      Good space distribution is necessary to support logic circuit
additions while minimizing perturbation to previously placed circuits
on the chip.  Also, increases in circuit sizes to enhance performance
may require additional nearby space.  A third benefit is that
resolution of overlaps during circuit placement is made easier by
keeping the empty space distributed.

      The following steps are required to implement this technique:
     1.  The chip area is divided into regions.  The figure shows one
example of a chip divided into 100 regions of equal size.
     2.  A metric is defined for the circuit placement program which
describes the ce...