Browse Prior Art Database

Programmable Support for Controlling Memory Subsystem Configurations in Personal Computers

IP.com Disclosure Number: IPCOM000107537D
Original Publication Date: 1992-Mar-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 4 page(s) / 169K

Publishing Venue

IBM

Related People

Ozaki, BM: AUTHOR [+3]

Abstract

Described is a software facility that provides improved flexibility in personal computers for address mapping, mode support, and module support. The facility enables systems to expand memory configurations and to provide dynamic reconfiguration upon error detection.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 46% of the total text.

Programmable Support for Controlling Memory Subsystem Configurations in Personal Computers

       Described is a software facility that provides improved
flexibility in personal computers for address mapping, mode support,
and module support.  The facility enables systems to expand memory
configurations and to provide dynamic reconfiguration upon error
detection.

      Typically, personal computer memory subsystems have operated in
a single mode, either interleaved or non-interleaved, and with single
types of memory chips, such as 256K, 1M, or 4M chips.  Also, a fixed
correspondence exists between the memory address and the physical
location of the memory, i.e.,  an address range is always mapped to a
particular set of memory modules.  In addition, different types of
memory chips require that the correspondence between memory modules
and memory addresses be fixed or a separate control logic will be
required for each type of memory module.  Often mechanical switch
settings are required to set the memory addresses.  Some memory cards
have registers for the starting address of the memory which can be
changed dynamically. However, the memory cards do not support
multiple modes of operation or multiple types of memory modules.

      Interleaving has been used in large systems to increase the
performance of the memory subsystem.  However, interleaving limits
the minimum amount of memory that can be added to a system and
requires the de-allocation of larger amounts of memory when an error
is detected.  For a two-way interleaved system, twice as much memory
is de-allocated when an error is detected as for a non-interleaved
system.  As more and more memory is added to the system, there is a
need to support flexible memory configurations for expansion and to
provide dynamic reconfiguration upon error detection.

      The concept described herein utilizes a random-access memory
(RAM) macro or a bank of registers controlled by a memory controller
to provide flexibility in address mapping, mode support and module
support.  The RAM macro is organized so that each row corresponds to
a different address space. The columns within the row specify the
physical memory modules to which the address is mapped, the size of
the memory modules, and the mode of operation.  The register bank is
organized so that each register corresponds to a different address
space and the bits within the register specify the physical memory
modules to which the address is mapped, the size of the memory
modules, and the mode of operations.  Each row or register may be
programmed independently.  Multiple modes and module sizes may be
supported by the same memory controller.  The RAM macro is accessed
during each memory transfer and the data is used to control the
memory interface logic.  The columns in the RAM macro or the bits in
the register may be extended to support other system variables, such
as module speed, error checking, or cacheability.

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