Browse Prior Art Database

Many Snap

IP.com Disclosure Number: IPCOM000107541D
Original Publication Date: 1992-Mar-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 7 page(s) / 302K

Publishing Venue

IBM

Related People

Delgado-Frias, JG: AUTHOR [+3]

Abstract

The computational tasks to be implemented by the neurocomputer architecture described in this article are specified by equation 1, as from (1), (Image Omitted) where N is the number of neurons in the neural network, assumed to be a power of 2 for simplicity of discussion unless otherwise stated, the subscripts on the weights W such as W13 is to be interpreted as meaning the weight of the connection from neuron 3 to neuron 1, Yj is the jth neuron output value connected to one of the ith neuron's inputs through a connection weight Wij, and F(zi), where zi is the summation over N of the WijYj products, represents the neuron activation function e.g., the non-linear sigmoid function (2).

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Many Snap

       The computational tasks to be implemented by the
neurocomputer architecture described in this article are specified by
equation 1, as from (1),

                            (Image Omitted)

where N is the number of neurons in the neural network, assumed to be
a power of 2 for simplicity of discussion unless otherwise stated,
the subscripts on the weights W such as W13 is to be interpreted as
meaning the weight of the connection from neuron 3 to neuron 1, Yj is
the jth neuron output value connected to one of the ith neuron's
inputs through a connection weight Wij, and F(zi), where zi is the
summation over N of the WijYj products, represents the neuron
activation function e.g., the non-linear sigmoid function (2).

      In this article, it is assumed that the neural network of N
neurons is completely connected requiring four basic operations for
neural network emulation, namely, N2 multiplications, N product
summations, N activation functions, and N x N communications.  The
SNAP (Scalable Neural Array Processor) architecture (3) implements
the four basic neural network emulation operations as specified by
equation 1, providing the multiplication operations by utilizing N2
multipliers, the product summations by using 2N pipelined adder tree
structures, the activation functions by using 2N activation modules,
and the N x N communications by utilizing the same 2N pipelined adder
tree structures in a reverse communication manner.  The combined
function of summation and reverse communication included within the
same tree structure lends the name of Communication Adder Tree (CAT).
Due to the massive parallel nature of SNAP, a bit-serial
representation is assumed for large N implementations.

      Since 2N CATs and 2N Sigmoid generators are utilized in SNAP
with the multipliers associated with N neurons, i.e., N2 multipliers,
full utilization of the multipliers, CATs, and sigmoid generators
during their calculation times can be obtained by simultaneously
emulating four neural networks each containing N/2 neurons.  Four
neural networks of N/2 neurons each requires a total of 4(N/2)2=N2
multipliers and 4(N/2) or 2N CATs and sigmoid generators.  Other
combinations of the number of neural networks and the number of
neurons in each can be emulated simultaneously on the modified SNAP
structure with varying component utilization efficiencies.  Using a
simple example to describe the concepts involved, assume B is equal
to the number of neural networks to be emulated and each network
contains the same number of neurons, (m).  For a SNAP designed to a
specified size of N, B neural networks can be emulated with full
utilizing of the multipliers, CATs, and sigmoid generators if B*(m)
equals 2N and if B* (m2)=N2 .  Different utilization efficiencies
will result if both relationships are not met.  For example, B = 1
and m = N, then full multiplier efficiency is obtained, B*(m2)=N2,
but only 50% utili...