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Browse Prior Art Database

Shared Output Snap

IP.com Disclosure Number: IPCOM000107542D
Original Publication Date: 1992-Mar-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 4 page(s) / 183K

Publishing Venue

IBM

Related People

Delgado-Frias, JG: AUTHOR [+3]

Abstract

The computational tasks to be implemented by the neurocomputer architecture described in this article are specified by equation 1, as from (1), (Image Omitted) where N is the number of neurons in the neural network, assumed to be a power of 2 for simplicity of discussion unless otherwise stated, the subscripts on the weights W such as W13 is to be interpreted as meaning the weight of the connection from neuron 3 to neuron 1, Yj is the jth neuron output value connected to one of the ith neuron's inputs through a connection weight Wif, and F(zi), where zi is the summation over N of the WijYj products, represents the neuron activation function, e.g., the non-linear sigmoid function (2).

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 43% of the total text.

Shared Output Snap

       The computational tasks to be implemented by the
neurocomputer architecture described in this article are specified by
equation 1, as from (1),

                            (Image Omitted)

where N is the number of neurons in the neural network, assumed to be
a power of 2 for simplicity of discussion unless otherwise stated,
the subscripts on the weights W such as W13 is to be interpreted as
meaning the weight of the connection from neuron 3 to neuron 1, Yj is
the jth neuron output value connected to one of the ith neuron's
inputs through a connection weight Wif, and F(zi), where zi is the
summation over N of the WijYj products, represents the neuron
activation function, e.g., the non-linear sigmoid function (2).

      In this article, it is assumed that the neural network of N
neurons is completely connected requiring four basic operations for
neural network emulation, namely, N2 multiplications, N product
summations, N activation functions, and N x N communications.  The
SNAP (Scalable Neural Array Processor) architecture (3) implements
the four basic neural network emulation operations as specified by
equation 1, providing the multiplication operations by utilizing N2
multipliers, the product summations by using 2N pipelined adder tree
structures, the activation functions by using 2N activation modules,
and the N x N communications by utilizing the same 2N pipelined adder
tree structures in a reverse communication manner.  The combined
function of summation and reverse communication included within the
same tree structure lends the name of Communication Adder Tree (CAT).
Due to the massive parallel nature of SNAP, a bit-serial
representation is assumed for large N implementations.

      In the original SNAP architecture (3) one set of N CATs and
sigmoid generators is idle while the other set of N CATs and sigmoid
generators is active.  Since there is no overlap in the utilization
of either set of N sigmoid generators the output of the two sets of N
CATs can be shared by one set of N sigmoid generators.  A further
modification to the original SNAP entails setting one set of N CATs
to provide only the accumulation function and the other set of N CATs
to provide only the communication's function.  The resulting
structure utilizes N2 multipliers, N accumulation trees, N sigmoid
generators, and N communication trees and is termed the Shared Output
SNAP.

      Full details on the SNAP structure and its operation can be
found in (3).  The multipliers, CATs, and sigmoid generators require
a modification to support the Shared Output SNAP operation and
maintain the original performance characteristics for a network
emulation of N neurons.  The multipliers do not require a bypass path
using instead a dedicated input source from the communication trees
and a dedicated output to the accumulation trees.  The vertical CATs
are modified by the removal of the reverse communicat...