Browse Prior Art Database

Parallel Processing System with Crosspoint Switch

IP.com Disclosure Number: IPCOM000107563D
Original Publication Date: 1992-Mar-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 4 page(s) / 166K

Publishing Venue

IBM

Related People

Blum, A: AUTHOR [+6]

Abstract

Described are conceptional enhancements for the continuous availability of a parallel processing system with a crosspoint switch.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Parallel Processing System with Crosspoint Switch

       Described are conceptional enhancements for the
continuous availability of a parallel processing system with a
crosspoint switch.

      Fig. 1 shows several (n) processing units with an n x n
crosspoint switch matrix allowing any processing unit to communicate
with any other processing unit.  Not all of the interconnected units
have to be processing units; other hardware can also be connected to
the crosspoint switch, providing shared facilities accessible by any
one of the processing units.  Such hardware may be equipped with
several ports to the crosspoint switch, which allows shared
simultaneous access by several processing units.  As can also be seen
from Fig. 1, each processing unit comprises a local memory capable of
accommodating the associated operating system.

      To improve on-line fault detection for higher data integrity,
the entire parallel processing system or part of it can be arranged
in pairs of identical processing units running the same application
program concurrently and comparing the results after they have been
communicated through the crosspoint switch.

      Since the crosspoint switch allows a high data rate and fast
non- blocking access, it is conceivable to compare the communicated
results by means of the receiving processing units as a first
alternative.  For this purpose, the information of the sending
processor pair is communicated to the destination processor pair
through the crosspoint switch according to the following algorithm
(Fig. 2).

      The information resulting from process A is consecutively
transmitted to both destination processes of the destination
processor pair via the single crosspoint switch.  In addition, the
information resulting from process A', executed on a duplicated
processor, has to be sent to both destination processors provided for
running identical processes B and B'.  The information streams are
stored in the local memories of the processors and compared by the
respective processors from their memories.

      In order to enhance the overall performance, the compare
function should be implemented in hardware as a second alternative.
Such a hardware compare circuit may be a single facility connected to
two ports of the switch and shared sequentially by different pairs of
processing units (Fig. 3).

      As can be seen from Fig. 3, the output signal of the compare
circuit is used to identify a possible fault of one of the processing
units within the individual concurrently running pair of units
without knowing which one is faulty. The faulty result is...