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I/O Logic Test

IP.com Disclosure Number: IPCOM000107567D
Original Publication Date: 1992-Mar-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 2 page(s) / 59K

Publishing Venue

IBM

Related People

Diebold, U: AUTHOR [+8]

Abstract

A second, 'external' boundary scan shift register latch chain (BSC) can be used to supplement the existing 'internal' BSC for improving the test coverage of a logic chip or module. Fig. 1 shows a tester 10 connected to a chip or module 20 under test. Chip or module 20 contains a number of logic channels 25 which are to be tested. Tester 10 contains timed tester channels 30 for performing the logic tests on the chip and parametric tester channels 40 for the parametric tests. The tester further includes a performance board 70 which is connected between tester 10 and chip or module 20.

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I/O Logic Test

       A second, 'external' boundary scan shift register latch
chain (BSC) can be used to supplement the existing 'internal' BSC for
improving the test coverage of a logic chip or module.  Fig. 1 shows
a tester 10 connected to a chip or module 20 under test.  Chip or
module 20 contains a number of logic channels 25 which are to be
tested.  Tester 10 contains timed tester channels 30 for performing
the logic tests on the chip and parametric tester channels 40 for the
parametric tests.  The tester further includes a performance board 70
which is connected between tester 10 and chip or module 20.

      The multiplexer 60 in the performance board 70 serves to switch
the input/output (I/O) pins 90 of chip or module 20 between the
parametric tester channels 40 and the external BSC 50, thus allowing
both parametric testing and - by scanning test values into the
external BSC 50 - timed testing of the I/O books 80.

      As shown in Fig. 2, the concept of the external BSC can be
extended to STUMPS testing.  In this figure, the same reference signs
as in Fig. 1 are used for the same features. The circuit additionally
incorporates a programmed random pattern generator (PRPG) 100 and a
multiple input signature register (MISR) 110 which are controlled by
the clock (CLK) and control (CONTR) signals from the timed tester
channels 30.  The test data for the external BSC 50 is fed from
(PRPG) 100.  In response to stimuli from (PRPG) 100 and sensing by
(M...