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Combined Sense Amplifier and Decoder

IP.com Disclosure Number: IPCOM000107569D
Original Publication Date: 1992-Mar-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 2 page(s) / 65K

Publishing Venue

IBM

Related People

Behnen, E: AUTHOR [+4]

Abstract

Fig. 1 shows a sense amplifier and decoder. Bit lines BL0-BL3 are connected to the gates of transistors T2-T5 which form one half (the left half) of the differential sense amplifier. The other half (the right half) of the differential sense amplifier is comprised of transistor T1 which has a longer channel than transistors T2-T5. The gates of transistors T7-T10 are connected to lines CS0-CS3 carrying the column select signals. A bit line is therefore selected by applying a signal to one of the lines CS0-CS3 which turns on the corresponding transistor T7-T10. This makes one of the paths conductive to form the left half of the differential amplifier and allows the signal generated on the bit line to be read through the output ports DOC, DOT.

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Combined Sense Amplifier and Decoder

       Fig. 1 shows a sense amplifier and decoder.  Bit lines
BL0-BL3 are connected to the gates of transistors T2-T5 which form
one half (the left half) of the differential sense amplifier.  The
other half (the right half) of the differential sense amplifier is
comprised of transistor T1 which has a longer channel than
transistors T2-T5.  The gates of transistors T7-T10 are connected to
lines CS0-CS3 carrying the column select signals.  A bit line is
therefore selected by applying a signal to one of the lines CS0-CS3
which turns on the corresponding transistor T7-T10.  This makes one
of the paths conductive to form the left half of the differential
amplifier and allows the signal generated on the bit line to be read
through the output ports DOC, DOT.  This arrangement has the
advantage that capacitive load and path resistance are moved from the
heavily loaded bit line to the fast switching output nodes of the
amplifier.

      Fig. 2 shows a further refinement of the idea in which a sense
amplifier is formed with a 1-in-8 decoder.  Figs. 1 and 2 use the
same reference signs to indicate the same devices.  The suffix A or B
denotes whether the device is connected to port A or port B.  The
decoder is built up of two branches, each of which is formed from a
circuit similar to that shown in Fig. 1.  Additionally, in order to
balance the load on the circuit, each of the selection devices
(T2-T5) is complemented so as to bal...