Browse Prior Art Database

Spare I/O Preparation for Use at Release Interface Tape B

IP.com Disclosure Number: IPCOM000107570D
Original Publication Date: 1992-Mar-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 5 page(s) / 197K

Publishing Venue

IBM

Related People

Dillinger, TE: AUTHOR [+6]

Abstract

It is critical to reduce product design cycles in order to minimize time to market. With latest CMOS technologies, the release interface tape (RIT) process can be broken into two passes: RIT A, the initial substrate RIT which needs significant turn-around time (TAT), and RIT B, the personalization RIT which completes logic structuring and connection and takes minimal TAT. Pin assignments and drivers must be correct at RIT A time, but all internals can be restructured and reconnected at RIT B time. For fast engineering change (EC) RITs also, the goal is to have repairs only require RIT B-type changes. A method is needed by which unforeseen driver interface changes could be accommodated with only RIT B updates by preparing drivers and receivers on spare I/O at RIT A time.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 42% of the total text.

Spare I/O Preparation for Use at Release Interface Tape B

       It is critical to reduce product design cycles in order
to minimize time to market.  With latest CMOS technologies, the
release interface tape (RIT) process can be broken into two passes:
RIT A, the initial substrate RIT which needs significant turn-around
time (TAT), and RIT B, the personalization RIT which completes logic
structuring and connection and takes minimal TAT.  Pin assignments
and drivers must be correct at RIT A time, but all internals can be
restructured and reconnected at RIT B time.  For fast engineering
change (EC) RITs also, the goal is to have repairs only require RIT
B-type changes.  A method is needed by which unforeseen driver
interface changes could be accommodated with only RIT B updates by
preparing drivers and receivers on spare I/O at RIT A time.

      Drivers and receivers must be specified at RIT A time.
Different drivers and receivers are involved with control I/O than
boundary scan I/O, as well as with particular voltage levels, such as
ECL versus TTL.  With a limited number of spare I/O generally, the
user must gauge his highest exposures for needed signals and set up
spare I/O in preparation for these cases.

      Guidelines for spare I/O preparation in order to meet these
goals are the following:
-  Model spare I/O as common I/O.  This allows their use as either an
input or an output or both with RIT B updates.
-  Connect any spare MCM pins into spare I/O networks, too, in case
an off-module need arises.
-  Connect spare I/O between as many chips as possible on the module
to maximize preparation for unforeseen signal connections needed.
-  Focus network types on the most likely additions, i.e., data nets,
but if sufficient spare I/O are available, set up a few spare control
I/O nets as well.

      The logical configuration of preparing spare I/O has just the
two flavors, i.e., control net or data net, used to prepare for
anticipated needs with legal driver/receiver configurations.  The
data nets are standard series boundary scan interfaces and the
control nets are non-boundary scan. (The series boundary scan logic
configuration, which we will reference as a single box in Fig. 2, is
shown in Fig.  1.)

      Data nets would be set up as CIO drivers with series boundary
scan on all chip sources to a spare I/O net.  (See Fig. 2.)  This net
can participate in interconnect testing just like any true functional
bidirectional interconnection. The chip internal logic connections to
the boundary books will have all the clock, scan, and driver inhibit
hookups as other boundary books.  The only variation will be that the
driver data and enable data inputs will be tied to an internal
termination state.  The enable input must be terminated to the off
state.  For the ease of shared connections, the data input could be
tied to this same state.  (The data is being tied only for the
purposes of a clean EDS model and fu...