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Combined Sense Amplifier and LSSD Latch

IP.com Disclosure Number: IPCOM000107571D
Original Publication Date: 1992-Mar-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 1 page(s) / 31K

Publishing Venue

IBM

Related People

Behnen, E: AUTHOR [+4]

Abstract

The figure shows a combined sense amplifier and LSSD latch. Cross- coupled p-type transistors T1, T2 and cross-coupled n-type transistors T3, T4 are placed between the first stage and the second stage of a sense amplifier to form a latch which latches the signals received on DOC and DOT from the first stage. During precharge of the sense amplifier with signal PCD, this latched data is transferred to the cross-coupled p-type devices T5 and T6 from where it can be read out through port DOUT.

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Combined Sense Amplifier and LSSD Latch

       The figure shows a combined sense amplifier and LSSD
latch. Cross- coupled p-type transistors T1, T2 and cross-coupled
n-type transistors T3, T4 are placed between the first stage and the
second stage of a sense amplifier to form a latch which latches the
signals received on DOC and DOT from the first stage.  During
precharge of the sense amplifier with signal PCD, this latched data
is transferred to the cross-coupled p-type devices T5 and T6 from
where it can be read out through port DOUT.

      The combined sense amplifier and LSSD latch also contains a
slave latch formed from p- and n-type transistors, as shown in the
figure, and a shift input. Thus, the sense amplifier can form part of
a chain of sense amplifiers from which the data can be clocked out.