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Browse Prior Art Database

Auto-thresholding Receiver System

IP.com Disclosure Number: IPCOM000107577D
Original Publication Date: 1992-Mar-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 3 page(s) / 110K

Publishing Venue

IBM

Related People

Cecchi, DR: AUTHOR [+2]

Abstract

Most computer systems have internal data buses that are long physically and heavily loaded. Examples of this would be buses to mainstore memory or I/O processors. Special circuits called off chip drivers (OCDs) are designed to drive these large loads. Several problems arise which must be considered by the designer of these drivers. First, the drivers must have controlled turn-on rates to reduce noise. Second, the drivers must be capable of sourcing relatively large amounts of current to produce a voltage change large enough to be recognized by receiver circuits on the bus.

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This is the abbreviated version, containing approximately 52% of the total text.

Auto-thresholding Receiver System

       Most computer systems have internal data buses that are
long physically and heavily loaded.  Examples of this would be buses
to mainstore memory or I/O processors.  Special circuits called off
chip drivers (OCDs) are designed to drive these large loads.  Several
problems arise which must be considered by the designer of these
drivers.  First, the drivers must have controlled turn-on rates to
reduce noise. Second, the drivers must be capable of sourcing
relatively large amounts of current to produce a voltage change large
enough to be recognized by receiver circuits on the bus.

      This invention addresses the problem in terms of the receiver
logic thresholds and provides for acceptance of a lower threshold for
rising signals and a higher threshold for falling signals.

      This invention implements the receiver function with two
receivers, one which switches at a high voltage, the other which
switches at a low voltage.  (Refer to Figs. 1 and 2.)  The two
receivers each receive the same signal from the chip input.  The two
receiver outputs are wired to a selector (such as an AND/OR circuit).
The controlling signal to the selector comes from a latch that
"remembers" the data from the previous cycle.  If the previous cycle
had the bus line "low", the selector will gate the low-threshold
receiver through to the internal chip logic.  If the previous cycle
had the bus line "high", the selector will gate the high-threshold
receiver through to the internal chip logic.  It is necessary to make
sure the latch is initialized.  This can be done easily by holding
the data input low (or high) for several cycles to guarantee it
achieved a level that both receivers recognize as the same value.

      Threshold levels in CMOS receivers can be adjusted in the
circuit design by controlling the relative P-channel to N-channel
strength.  The strength is defined by tailoring the width/length
ratios of the FETs.  The high threshold receiver would have a
relatively strong P-channel device, the low threshold receiver would
have a relatively strong N-channel device, assuming the receiver is a
simple CMOS inverter comprised of a single NFET and PFET.  If only
N-channel devi...