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Logic Mapping Representation that Allows Automatic Silicon Compilation

IP.com Disclosure Number: IPCOM000107593D
Original Publication Date: 1992-Mar-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 8 page(s) / 351K

Publishing Venue

IBM

Related People

Correale Jr, A: AUTHOR

Abstract

Logic capture for complex functions is generally accomplished in a number of ways: 1. Direct, using schematic diagram symbols, i.e., AND, NOR (gate level) 2. Boolean equation 3. High-level behavioral language 4. Picture mapping, i.e., arrays

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Logic Mapping Representation that Allows Automatic Silicon Compilation

       Logic capture for complex functions is generally
accomplished in a number of ways:
      1. Direct, using schematic diagram symbols, i.e., AND,
      NOR (gate level)
      2. Boolean equation
      3. High-level behavioral language
      4. Picture mapping, i.e., arrays

      The physical realization of these functions can be done either
manually or automatically via silicon compilation. The level of
sophistication of the compilation algorithm generally dictates the
efficiency of the silicon realization.  Schematic capture
representation can improve the efficiency of the compilation and even
aid in creating a more efficient logical and physical realization.
This article describes a logical mapping process for a barrel
shifter/rotator with enhanced features which allows physical
compilation using auto-macro generation techniques.

      Fig. 1 illustrates the symbolic representation of a 16-bit (HW)
barrel rotator.  This representation is for a LSB (bit F) to MSB (bit
0) direction of rotation (rotate left).

      The 16 data input bits 0-9, A-F, are shown on the left side of
Fig. 1.  The 16-character input string associated with each of the
respective data inputs represents the resulting input bit steering to
each of the 16 outputs for each potential rotate operation.  For
example, the lower-most line entry, 0-9, A-F, is connected to output
0. The next line entry above the lowest, 1-9, A-F, 0, is connected to
output 1 and so on.  For a rotate by 0 bit positions, e.g., no
rotate, the outputs 0-9, A-E, F would receive data from inputs 1-A,
B-F, 0, respectively.  For a 15-bit rotate, the outputs 0, 1-A, B-F
would be receive data from inputs F, 0-9, A-E, respectively.

      Fig. 2 illustrates the symbolic representation of a 16-bit
shift left shifter (LSb to MSb).  All bits of lesser significance
than the nth bit are set to '0' ('1') for an n bit shift for
positive (negative) logic realizations.

      Fig. 2 is arranged in the same manner as Fig. 1.  For a shift
by 0 bit positions, e.g., no shift, the outputs 0-9, A-F would
receive data from inputs 0-9, A-F, respectively. For a shift by 1 bit
position, the outputs 0-9, A-E, F would receive data from inputs 1-A,
B-F, g, respectively.  For a 15-bit shift, the outputs 0, 1-9, A-F
would receive data from inputs F, for output bit 0, and 'g' for all
other outputs.

      Fig. 3 illustrates the symbolic representation of a 16-bit
shift left shifter with byte shift capability for each of the two
bytes.  This representation is for a LSB to MSB direction of shift.
In this case, the LSBs are F and 7 for the Least Significant and Most
Significant Bytes, respectively.  All bits of lesser significance
than the nth bits of each byte are set to '0' ('1') for an n
bit shift for positive (negative) logic realizations.  For a byte
shift by 0 bit positions, e.g., no shi...