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Transmit Data Control Block Structure Defined to Optimize Performance of a High Level Data Link Controller Running in a Layered Microcode Environment

IP.com Disclosure Number: IPCOM000107597D
Original Publication Date: 1992-Mar-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 5 page(s) / 226K

Publishing Venue

IBM

Related People

Farrell, JK: AUTHOR [+5]

Abstract

This article describes a technique for transmitting data control block (DCB) structure defined to optimize performance and function for an integrated direct memory access (DMA) function of a high-level data link controller (HDLC) running in a layered microcode environment.

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Transmit Data Control Block Structure Defined to Optimize Performance of a High Level Data Link Controller Running in a Layered Microcode Environment

       This article describes a technique for transmitting data
control block (DCB) structure defined to optimize performance and
function for an integrated direct memory access (DMA) function of a
high-level data link controller (HDLC) running in a layered microcode
environment.

      The integrated DLC (IDLC) chip supports linked array chaining
on the transmit DMA controller.  Transmit linked array chaining
allows data to be DMAed out of multiple IOP data buffer segments on a
particular channel.  When the channel is configured to run an HDLC
protocol, the data from multiple I/O processor (IOP) data buffer
segments will be concatenated together to form a single HDLC frame.
Also, transmit linked array chaining allows for multiple frames to be
chained together.  This enables multiple frames, which the IOP
microcode has placed in memory, to be sent without code intervention
between frames.

      Transmit linked array chaining operates using DMA control
blocks (DCBs).  DCBs are three word, contiguous blocks in IOP memory.
DCBs can be discontinuous, relative to other DCBs, in storage.  The
data length and data PTR for the first data buffer of a transmit
chain are pointed to by writing to internal IDLC registers.  The
first DCB pointer is written to an internal IDLC register for the
transmit channel being run.  The IDLC uses this DCB pointer to fetch
the first DCB.  An example of linked array chaining on the
transmitter is shown in block diagram Fig. 1.

      Transmit DMA configuration registers TDCR1 -  TDCR4 are shown
in Fig. 2.  These registers are used to set up the transmit DMA
controller (TDMAC).  TDCR1 describes the size of the first buffer
segment.  TDCR2 is used to initialize the internal FIFO.  TDCR3
provides a pointer to the first buffer segment.  TDCR4 provides a
pointer to the DCB which points to the next buffer segment, and
describes how the data is to be framed, and the position of the
buffer in the DMA chain.
@    Transmit DMA Byte Count (TDBC) - 16 bits
      -    This value defines the length in bytes of the current data
buffer (pointed to by TDBA).  All values in the range of '0000'H to
'FFFF'H bytes are valid.  A value of '0000'H causes an immediate
fetch of the DCB pointed to by DCBA.
@    Transmit DMA Buffer Address (TDBA) - 24 bits
      -    This field points to the current data buffer to be
transmitted.  The data buffer can be located on any byte boundary;
because of the 24-bit address, however, it is recommended that the
buffer segment be on an even-word (4 byte) boundary.
           Since the IDLC only performs full-word operations,
specifying an address which is not on an even-word boundary results
in only part of the word being usable. For example, if the address
specified was 'xxxxx3', the IDLC would f...